Thanks Piotr
Do you have sample code or scheme? I think I use ethernet controller
and M16C 62P group processor.

icegray wrote:

> This is not fun If I can do it I'll earn money (I hope). I must make
> network for up to 100 devices and every device need 2.5Mbit/s so I
> think this is not simple.

Are you sure you really need Ethernet? Perhaps the
old good RS485 will do -- it is a lot easier and cheaper,
but its  bandwidth is comparable to Ethernet's (i.e. 10Mbit/s).

    Best regards
    Piotr Wyderski

icegray wrote:

> I want to implement ethernet but I have no exprience about ethernet.

First of all: why do you want to implement an Ethernet controller
inside an FPGA chip if there are many specialized chips on the
market? FPGA-based peripherals are very expensive (compared
to their specialized counterparts), so generally it's not a good idea
to buy a larger FPGA chip just to insert popular peripherals (Ethernet,
USB etc.) into it. FPGAs are good for reconfigurable circuits, high
speed datastream signal processing, driving specialized peripherals
(LCDs, CODECs, ADCs etc.), but not for reinventing the wheel. :-)

> What should i do?

Buy RTL8019 or CS8900 and forget about the problem?

    Best regards
    Piotr Wyderski

It depends on your synthesis tool.
I do my synthesis with Precision + ISE for Xilinx and with Quartus for
Altera. There are no special commands required to synthesise verilog
files.
You only have to add the verilog files to your synthesis project like your
vhdl files.
It's really very easy.

Are there additional command or setup? Can I syntesis without problem
as writing vhdl component?

Hi,

yes you can.
Mixed languages designs are no problem.
You can instanciate a verilog component inside a vhdl unit without any
problems.

Hi AVG,
(http://www.opencores.com/proje=ADcts.cgi/web/ethmac/overview) is
verilog? I can write VHDL, can I use it as component?

Thanks Berty
This is not fun If I can do it I'll earn money (I hope). I must make
network for up to 100 devices and every device need 2.5Mbit/s so I
think this is not simple. I want to run 10 devices together now. Your
I2C example is very good. You can recommend Eth Mac (I think this is
ethernet controller like as RTL8100). If I you Eth Mac I think I can
done for a month.

Hi,

take a look at Opencores Ethernet mac
(http://www.opencores.com/projects.cgi/web/ethmac/overview)
It's easy to use and works very well.
I have used this core in several projects with great success. You only
need an external Phy connected to the FPGA (e.g. Intels LXT971A). The
businterface to external uc is a wishbone bus (defined by opencores). 

Designing a Eth Mac while have its own challenges it is not "too"
difficult, however you need to consider two thing first -
Base on how much experience you have it can take from few weeks to few
years.
What requirement you have for the Mac which can be as very simple or
very complicated.
For example even a simple question like do you need to support half
duplex can add to the complexity not to mention learning etc.
(Incase you are not familiar with Eth at all using the I2C you design
there are as you now know several I2C controller, a slave only a master
only a combination a master that support clock stretching, a master
that support multi master, a master/slave that support 10 bit
addressing, higher speed like 400K or 3.4M and so on, a simple slave
you can probably finish in a day or two again depend on your experience
however a complete full blast master with all the feature will take you
a longer and of course the more features the more time you also spend
on verification and building the verifiers)
If this design is just for your own fun than go ahead if not do
consider buying of the shelf Eth Mac there are plenty of flavor out
there which will probably cost you less money and time than any other
solution you can come with FPGA or cpu.
Have Fun.