nospam@nospam.com wrote:
> My aim is, other than understanding state machines at a
> intuitive level, to write them in the most efficient way.
> 
> When I'm writing combinational code, I know when it will
> end up in too many logic gates.. same for sequential, but
> for state machines the "black box" is actually into my
> mind.
> 
> Many Thanks in advance for any attempts to illuminate me.
> 
> Greets,
> Mike
> 

Mike-

One thing you could do is download one of the free synthesis tools from 
Xilinx or Altera and write a couple simple machines, then look at the 
schematic version of their product.  For simple machines, it should be 
pretty easy to see what the tool did.

    Jake

http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Seq/impl.html
or just type "Mealy Moore" in google search
Aurash
nospam@nospam.com wrote:

>Hi all,
>
>I'm a low-level kind of programmer (and wannabe hardware
>designer). When I write a piece of code, be it assembly,
>C or Verilog, I need to have a precise idea of how it
>will end up.
>I've began to explore the wonderful world of FPGAs and
>of the Verilog hardware description language, and while
>I do understand that combinational logic can be reduced
>to its minimum terms, and I also understand latches and
>other sequential logic, I have big problems in figuring
>how a state machine ends up ("schematically speaking").
>
>Although I've hunted for, and found, some schematics of
>state machines, I still haven't found a clear explanation
>and description of them that makes me sleep at night. ;)
>
>My aim is, other than understanding state machines at a
>intuitive level, to write them in the most efficient way.
>
>When I'm writing combinational code, I know when it will
>end up in too many logic gates.. same for sequential, but
>for state machines the "black box" is actually into my
>mind.
>
>Many Thanks in advance for any attempts to illuminate me.
>
>Greets,
>Mike
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324

Hi all,

I'm a low-level kind of programmer (and wannabe hardware
designer). When I write a piece of code, be it assembly,
C or Verilog, I need to have a precise idea of how it
will end up.
I've began to explore the wonderful world of FPGAs and
of the Verilog hardware description language, and while
I do understand that combinational logic can be reduced
to its minimum terms, and I also understand latches and
other sequential logic, I have big problems in figuring
how a state machine ends up ("schematically speaking").

Although I've hunted for, and found, some schematics of
state machines, I still haven't found a clear explanation
and description of them that makes me sleep at night. ;)

My aim is, other than understanding state machines at a
intuitive level, to write them in the most efficient way.

When I'm writing combinational code, I know when it will
end up in too many logic gates.. same for sequential, but
for state machines the "black box" is actually into my
mind.

Many Thanks in advance for any attempts to illuminate me.

Greets,
Mike