Reply by Michael Dreschmann●May 28, 20052005-05-28
Hello,
I've an Virtex II (later it'll be a Spartan 3) witch is connected to
external asynchronous SRAM. Now I would like to access it in the same
way as a synchronous SRAM (like a BRAM for example). I think reading
should work in the same way as with an synchronous SRAM (set address
and /oe and read data at the next clock) as long the SRAM is fast
enough. But I've no idea how to implement a write access in an
efficient way. I could set address, data and /wr and create some logic
that clears the /wr signal at the falling edge of the clocksignal. But
so I could only use half the speed of the SRAM because the /wr signal
would only high for half the clock period.
Please let me know if there is any better way to implement this.
Michael