Thanx ppl.

Can I do something like we do with any spartan device, I mean without
using anything(Processor,IPs,Buses), can I map my application on
Virtex2Pro?

Thanx

Regards

sps

Chapter 4: Create and Import Peripheral Wizard of "Embedded System
Tools Reference Manual" (http://www.xilinx.com/ise/embedded/est_rm.pdf):

"The OPB/PLB peripheral (top design entity) template is in VHDL only. 
This is because the underlying library elements are implemented in
VHDL. The stub user-logic module template, however, can be in either
VHDL 
or Verilog to support a mixed-language development mode."

Additional verilog files can be used by adding them to the *.pao file of
the generated pcore.

Paul

sps wrote:
> 
> Hi,
> 
> I have a Verilog processing core. I want to implement it on Vertex2Pro
> device as a separate core , adding it to current bus architecture. I
> know that VHDL cores can be added.
> 
> Is it possible to add Verilog cores?
> 
> Thanks for the reply.
> 
> Regards
> 
> SPS

New version  of Xilinx  ISE Foundation (7.1i) supports mixed design
architectectures. So If you have one part of design in VHDL and other
parts in Verilog  you can it compile. 

Regards,
Amir

Hi,

I have a Verilog processing core. I want to implement it on Vertex2Pro
device as a separate core , adding it to current bus architecture. I
know that VHDL cores can be added.

Is it possible to add Verilog cores?

Thanks for the reply.

Regards

SPS