Reply by Adarsh Kumar Jain●June 22, 20052005-06-22
Hi All,
I am stuck with some JTAG interconnection tests on a board with 9 Xilinx
V2Pros and 2 Altera Stratixs.
I am using JTAG Technologies VIP Manager for the tests.
Somehow the tool / software is getting into errors as it sees 1's on the
GND net. I have digged into all possibilities as far as the software and
test generation is concerned but am unable to find the source. Maybe the
problem is on the hardware but the board works fine even if its failing the
JTAG Tests.
I know this is not the best place to put this question, but the support from
JTAG has been patchy ("you are not the only customers we have" kind of
response) and I feel that since a lot of you do board design and test, maybe
some of you can give me some pointers.
Thanks to all....
Adarsh Kumar Jain
CERN, Geneva