Hi Joseph..
First this guy works for a company and is allowed to get away with it?
It sounds like a true nightmare to even look at his code, let alone
interpret it!

But on the using blocking assingments in a non-clocked always block -
this was actually recommended to me on an advanced verilog course. The
only reason being given that it was more efficient to simulate. (don't
ask me to prove it!). It seems that it can be shown, for non clocked
always blocks the always event is triggered less times when blocking is
used. so at least he's doing *one* thing right. :)

Joseph H Allen wrote:
> In article <1119994796.827887.175030@g14g2000cwa.googlegroups.com>,
> Andy Peters <Bassman59a@yahoo.com> wrote:
> >Joseph H Allen wrote:
> >> In article <3iaqseFkg3klU1@individual.net>,
> >> Mike Treseler  <mike_treseler@comcast.net> wrote:
> >> >Joseph H Allen wrote:
> >>
> >> >> (if only you could use the blocking assign output as an input to another
> >> >> clocked always block... but you can't).
> >>
> >> >True. A blocking assignment is like a local variable.
> >> >However, you *can* make the always block as big
> >> >as you like with as many registers as you like.
> >>
> >> So... you should make the entire design in just one always block? :-)
> >>
> >> Verilog is a crazy language.  I write code in order, but you really don't
> >> have to:
> >>
> >> // Move ~c into a
> >>
> >> always @(b or c)
> >>   begin
> >>     a = b;
> >>     b = c;
> >>     b = ~c;
> >>   end
> >>
> >> A change in c triggers the always block: ~c moved into b.  Change in b
> >> retriggers the always block: b moved into a.  I guess synthesis tools have
> >> to make a dependency graph to figure out the dataflow.
> >
> >That sort of construct, with blocking variables, is bound to bite you
> >in the ass!
>
> I know someone who never ever makes more than one assignment to a variable
> in a single always block (no defaulting at all for maximized typing).
> Instead he makes an assignment to each register in each decision branch, so
> that you get one decision branch or less per editor screen: tiny state
> machines end up being 10,000 lines. He also uses non-blocking assigns in
> combinatorial always blocks, which is just weird.  He also does the out of
> order thing above: there will be some code at the end whose outputs are used
> by a state machine case at the top.  Finally, he never uses "if": only
> "casex", always with "// synthesis full_case parallel_case".  Usually, the
> casex's are three levels deep. Finally he always uses positional arguments
> in instantiations for modules with 100s of signals (sometimes the wire names
> even match the port names).  Oh yeah: he never uses parameters- only
> `defines all in one giant include file, even for state machine states.
> There is not one comment in 100,000 lines of code.  I am not making this up.
>
> Hmm... should I just edit the code and get it over with or should I make
> that Verilog refactoring program I always knew would come in handy...
> hmm...
>
> Well on the positive side, his_signals_look_like_this, NotLikeThis.  He uses
> the default emacs verilog mode, so the begins and ends are at the same
> indentation level.  Some other person's annoying code looks like this:
>
> if (theSignal) begin
>   stuff
> end // if (theSignal)
>
> Whoever wrote the elisp macros which put in these useless VHDLish comments
> should be shot.  His files all begin with a long boilerplate comment with no
> useful information (but he does put comments in his code, unlike the first
> person).
>
> Sorry, I'll stop ranting now.
> --
> /*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
> +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

In article <1119994796.827887.175030@g14g2000cwa.googlegroups.com>,
Andy Peters <Bassman59a@yahoo.com> wrote:
>Joseph H Allen wrote:
>> In article <3iaqseFkg3klU1@individual.net>,
>> Mike Treseler  <mike_treseler@comcast.net> wrote:
>> >Joseph H Allen wrote:
>>
>> >> (if only you could use the blocking assign output as an input to another
>> >> clocked always block... but you can't).
>>
>> >True. A blocking assignment is like a local variable.
>> >However, you *can* make the always block as big
>> >as you like with as many registers as you like.
>>
>> So... you should make the entire design in just one always block? :-)
>>
>> Verilog is a crazy language.  I write code in order, but you really don't
>> have to:
>>
>> // Move ~c into a
>>
>> always @(b or c)
>>   begin
>>     a = b;
>>     b = c;
>>     b = ~c;
>>   end
>>
>> A change in c triggers the always block: ~c moved into b.  Change in b
>> retriggers the always block: b moved into a.  I guess synthesis tools have
>> to make a dependency graph to figure out the dataflow.
>
>That sort of construct, with blocking variables, is bound to bite you
>in the ass!

I know someone who never ever makes more than one assignment to a variable
in a single always block (no defaulting at all for maximized typing). 
Instead he makes an assignment to each register in each decision branch, so
that you get one decision branch or less per editor screen: tiny state
machines end up being 10,000 lines. He also uses non-blocking assigns in
combinatorial always blocks, which is just weird.  He also does the out of
order thing above: there will be some code at the end whose outputs are used
by a state machine case at the top.  Finally, he never uses "if": only
"casex", always with "// synthesis full_case parallel_case".  Usually, the
casex's are three levels deep. Finally he always uses positional arguments
in instantiations for modules with 100s of signals (sometimes the wire names
even match the port names).  Oh yeah: he never uses parameters- only
`defines all in one giant include file, even for state machine states. 
There is not one comment in 100,000 lines of code.  I am not making this up.

Hmm... should I just edit the code and get it over with or should I make
that Verilog refactoring program I always knew would come in handy...
hmm...

Well on the positive side, his_signals_look_like_this, NotLikeThis.  He uses
the default emacs verilog mode, so the begins and ends are at the same
indentation level.  Some other person's annoying code looks like this:

if (theSignal) begin
  stuff
end // if (theSignal)

Whoever wrote the elisp macros which put in these useless VHDLish comments
should be shot.  His files all begin with a long boilerplate comment with no
useful information (but he does put comments in his code, unlike the first
person).

Sorry, I'll stop ranting now.
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Joseph H Allen wrote:
> In article <3iaqseFkg3klU1@individual.net>,
> Mike Treseler  <mike_treseler@comcast.net> wrote:
> >Joseph H Allen wrote:
>
> >> (if only you could use the blocking assign output as an input to another
> >> clocked always block... but you can't).
>
> >True. A blocking assignment is like a local variable.
> >However, you *can* make the always block as big
> >as you like with as many registers as you like.
>
> So... you should make the entire design in just one always block? :-)
>
> Verilog is a crazy language.  I write code in order, but you really don't
> have to:
>
> // Move ~c into a
>
> always @(b or c)
>   begin
>     a = b;
>     b = c;
>     b = ~c;
>   end
>
> A change in c triggers the always block: ~c moved into b.  Change in b
> retriggers the always block: b moved into a.  I guess synthesis tools have
> to make a dependency graph to figure out the dataflow.

That sort of construct, with blocking variables, is bound to bite you
in the ass!

-a

Joseph H Allen wrote:


> So... you should make the entire design in just one always block? :-)

It can be done.

http://www.designabstraction.co.uk/EXAMPLE/HTML/verilog.htm

     -- Mike Treseler

In article <3iaqseFkg3klU1@individual.net>,
Mike Treseler  <mike_treseler@comcast.net> wrote:
>Joseph H Allen wrote:

>> (if only you could use the blocking assign output as an input to another
>> clocked always block... but you can't).

>True. A blocking assignment is like a local variable.
>However, you *can* make the always block as big
>as you like with as many registers as you like.

So... you should make the entire design in just one always block? :-)

Verilog is a crazy language.  I write code in order, but you really don't
have to:

// Move ~c into a

always @(b or c)
  begin
    a = b;
    b = c;
    b = ~c;
  end

A change in c triggers the always block: ~c moved into b.  Change in b
retriggers the always block: b moved into a.  I guess synthesis tools have
to make a dependency graph to figure out the dataflow.
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Joseph H Allen wrote:

> (if only you could use the blocking assign output as an input to another
> clocked always block... but you can't).

True. A blocking assignment is like a local variable.
However, you *can* make the always block as big
as you like with as many registers as you like.

          -- Mike Treseler

Some more things which are OK, and which help with the single always block
style:

Multiple non-blocking assigns to the same register: the last one wins:

always @(posedge clk)
  begin
    out <= 0; // Normally low signal
    in_reg <= in;
    if (in && !in_reg)
      out <= 1; // Pulse out high for one cycle
  end

Mix blocking and non-blocking assigns:

always @(posedge clk)
  begin
    tmp = 0;
    if (condition)
      tmp = 1;
    if (other_condition)
      tmp = !tmp;
    out <= tmp;
  end

(if only you could use the blocking assign output as an input to another
clocked always block... but you can't).

I hate the two always block style: it requires too much typing.  It would be
cool if there was a tool to convert from one style to the other.

However, for FPGAs, there is one advantage to the two-always block style:
the Mealy outputs are handly to feed into block RAMs.  Block RAMs have short
setup requirements (but huge clk->out delays) so you can improve timing by
moving logic from the output side to the input side, if possible.

In article <4tSdnaiJvLdVeCLfRVn-iw@comcast.com>,
Mike Treseler  <mike_treseler@comcast.net> wrote:
>Davy wrote:
>
>> There is a problem on How to write FSM in
>> Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html).
>> Most synthesis tools recommend second "Using Two Always Blocks" style.
>> But I would like to use third "Single Always" style. It seems more
>> compact.
>
>It is. It works fine. Try it and see.
>
>> What's the pros and cons between the two styles? I see that the third
>> style may have state transition latency.
>
>A state transition takes one clock tick,
>no matter how you do it. Input synchronization
>should be handled as a separate issue.
>
>> But does the third style gain
>> higher frequency and shorter critical path? 
>
>There are no performance differences for
>synchronous designs.
>
>The single process controller does not allow
>unregistered outputs and makes long-winded
>textbooks unnecessary.
>
>
>         -- Mike Treseler.
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Hi Davy,

This is really a question for the synthesis tools on the matter of how your 
code is interpreted.
If any of the coding styles would produce different results, the 
corresponding synthesis tool should have fixed this deficiency by now :)

However, there is no really benefit in terms of what you will eventually 
get, but rather what is more convenient.
Personally, I always prefer a single "always", especially if the state 
machine has MANY outputs.

Going a bit further than your question, in my group, I am not enforcing any 
of those ways.
The coding style is completely at the designer's choice.
Instead, I enforce the designer to very-well document the "bubbles" stuff,
so that he knows what this state machine is doing and it is coded only once.

Hope this helps.

Vladislav



"Davy" <zhushenli@gmail.com> wrote in message 
news:1119850650.957024.310610@o13g2000cwo.googlegroups.com...
> Hi all,
>
> There is a problem on How to write FSM in
> Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html).
> Most synthesis tools recommend second "Using Two Always Blocks" style.
> But I would like to use third "Single Always" style. It seems more
> compact.
>
> What's the pros and cons between the two styles? I see that the third
> style may have state transition latency. But does the third style gain
> higher frequency and shorter critical path?
> Thanks!
>
> Best regards,
> Davy
> 

Davy wrote:

> There is a problem on How to write FSM in
> Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html).
> Most synthesis tools recommend second "Using Two Always Blocks" style.
> But I would like to use third "Single Always" style. It seems more
> compact.

It is. It works fine. Try it and see.

> What's the pros and cons between the two styles? I see that the third
> style may have state transition latency.

A state transition takes one clock tick,
no matter how you do it. Input synchronization
should be handled as a separate issue.

> But does the third style gain
> higher frequency and shorter critical path? 

There are no performance differences for
synchronous designs.

The single process controller does not allow
unregistered outputs and makes long-winded
textbooks unnecessary.


         -- Mike Treseler.

Hi all,

There is a problem on How to write FSM in
Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html).
Most synthesis tools recommend second "Using Two Always Blocks" style.
But I would like to use third "Single Always" style. It seems more
compact.

What's the pros and cons between the two styles? I see that the third
style may have state transition latency. But does the third style gain
higher frequency and shorter critical path? 
Thanks!

Best regards,
Davy