Good!
"MM" <mbmsv@yahoo.com> д����Ϣ����:3kspnkFvdd0qU1@individual.net...
> "Antti Lukats" <antti@openchip.org> wrote in message
> news:dc87bd$knm$03$1@news.t-online.com...
>>
>> they are NOT, available are only IEEE1532 files for XCFxxS not for XCFxxP
> !!
>
> OK, I see now what you mean. I assumed there was only one BSDL standard.
> Can
> you please explain what this IEEE1532 is all about compared to "regular"
> bsd
> files?
>
>
> Thanks,
> /Mikhail
>
>
Reply by Antti Lukats●July 28, 20052005-07-28
"MM" <mbmsv@yahoo.com> schrieb im Newsbeitrag
news:3kspnkFvdd0qU1@individual.net...
> "Antti Lukats" <antti@openchip.org> wrote in message
> news:dc87bd$knm$03$1@news.t-online.com...
> >
> > they are NOT, available are only IEEE1532 files for XCFxxS not for
XCFxxP
> !!
>
> OK, I see now what you mean. I assumed there was only one BSDL standard.
Can
> you please explain what this IEEE1532 is all about compared to "regular"
bsd
> files?
>
>
> Thanks,
> /Mikhail
>
there is one VERY BIG difference.
the IEEE1532 BSDL contains ALL the programming algorithm information needed
to program the device using IEEE1532 compatible Software. A plain BSDL file
does not contain this information. So if a company, (Xilinx as example) does
not publish some programming algorithm, but DOES publish the IEEE1532
compliant BSDL files for the device in question then you can either extract
the programming algorithm from IEEE1532 BSDL file or use IEEE1532 software
to programm the device in question. So that makes the difference very
important.
Xilinx promised the XCFxxP IEEE1532 BSDL files to be made available in 2006,
but to all my best knowledge the current (non-ES! ) XCFxxP silicon has
features that makes the XCFxxP not programmable in true plain IEEE1532
software, so Xilinx would not be able to deliver the XCFxxP IEEE1532 BSDL
files in 2006 unless they fix the silicon or the IEEE1532 standard. And even
if they fix the silicon by 2006, it still would not help me to program the
XCF08P today. Our client is waiting for solution. And will defenetly not
wait til 2006!!!
I am still waiting for the WebCases solutions, but so far nothing helpful. I
was promises of some sort of reply by monday. Lets see.
Antti
Reply by MM●July 28, 20052005-07-28
"Antti Lukats" <antti@openchip.org> wrote in message
news:dc87bd$knm$03$1@news.t-online.com...
>
> they are NOT, available are only IEEE1532 files for XCFxxS not for XCFxxP
!!
OK, I see now what you mean. I assumed there was only one BSDL standard. Can
you please explain what this IEEE1532 is all about compared to "regular" bsd
files?
Thanks,
/Mikhail
Reply by Antti Lukats●July 27, 20052005-07-27
"MM" <mbmsv@yahoo.com> schrieb im Newsbeitrag
news:3kpl5hFvlb6mU1@individual.net...
> "Antti Lukats" <antti@openchip.org> wrote in message
> news:dc5g2c$5dq$03$1@news.t-online.com...
> > "uxello" <uxello@free.fr> schrieb im Newsbeitrag
> > news:42e64094$0$20177$626a14ce@news.free.fr...
>
> > The first WebCase
> > we opened - the response from Xilixn was: - well there has been not much
> > interest in XCFxxP IEEE1532 BSDL files, so we have not made them. They
they are NOT, available are only IEEE1532 files for XCFxxS not for XCFxxP !!
Antti
Reply by MM●July 27, 20052005-07-27
"Antti Lukats" <antti@openchip.org> wrote in message
news:dc5g2c$5dq$03$1@news.t-online.com...
> "uxello" <uxello@free.fr> schrieb im Newsbeitrag
> news:42e64094$0$20177$626a14ce@news.free.fr...
> The first WebCase
> we opened - the response from Xilixn was: - well there has been not much
> interest in XCFxxP IEEE1532 BSDL files, so we have not made them. They are
> scheduled for 2006. You have to wait.
> JTAG Commands to force fpga load for
> XCFxxS
> CONFIG (11101110)
> XCFxxP
> XSC_CONFIG (0000000011101110)
>
Thank you Antti,
I've also found that I could also check the "Load FPGA"
option when I was generating the xsvf file. That's even
easier for me since i'm using XSVF player (XAPP058).
Uxello
Reply by Antti Lukats●July 26, 20052005-07-26
"uxello" <uxello@free.fr> schrieb im Newsbeitrag
news:42e64094$0$20177$626a14ce@news.free.fr...
> Hi all !
>
>
> I would like to make a Spartan 3 FPGA to reset and
> reprogram itself from a platform prom after I have
> reprogrammed the prom using JTAG boundery-scan.
>
> Is there any instruction I can send to the FPGA
> or the prom with JTAG to tell the FPGA to reprogram ?
> Usually this is done at power-on, but in my case,
> I can't power-off/on the whole system to make the
> FPGA to get a new firmware, and I can't reprogram
> the FPGA directly because it's required for the
> JTAG operation.
>
> Thank you
>
>
> Uxello
you can send 'config' command to the platform flash over JTAG if you
back-connect the JTAG to the FPGA or you may pull PROG_B low, in both cases
the reconfig would restart. We are doing similar thing where FPGA contains
PCI logic and JTAG port to its own platform flash. So the platform flash is
reprogrammed from JTAG interface that is in the FPGA and then same FPGA is
reconfigured with new bitstream.
unfortunatly we are using XCF08P and xilinx has some issues with it, so we
can reprogram the XCF08P but FPGA is not getting configured. We have opened
4 or 5 WebCases on this matter but not getting much help. The first WebCase
we opened - the response from Xilixn was: - well there has been not much
interest in XCFxxP IEEE1532 BSDL files, so we have not made them. They are
scheduled for 2006. You have to wait.
I assume you are using XCFxxS so hopefully you are doing better with it, to
my knowledge there are less or no problems with XCFxxS
JTAG Commands to force fpga load for
XCFxxS
CONFIG (11101110)
XCFxxP
XSC_CONFIG (0000000011101110)
always look at the BSDL files in Xilinx\xcfp\data\ !!
Antti
Reply by uxello●July 26, 20052005-07-26
Hi all !
I would like to make a Spartan 3 FPGA to reset and
reprogram itself from a platform prom after I have
reprogrammed the prom using JTAG boundery-scan.
Is there any instruction I can send to the FPGA
or the prom with JTAG to tell the FPGA to reprogram ?
Usually this is done at power-on, but in my case,
I can't power-off/on the whole system to make the
FPGA to get a new firmware, and I can't reprogram
the FPGA directly because it's required for the
JTAG operation.
Thank you
Uxello