Alessandro, this is a generic question, and Altera does not help you,
so I will:

Your temperature range is just Industrial, nothing special, just buy an
I-grade part.
You talk about "strong EMI interference". To me that sounds like the
outside world trying to influence the FPGA (not the FPGA radiating EMI.
That's a completely different issue).

A slow and single-ended oscillator signal is the worst thing to have,
making you sensitive to external noise. I would use a high-frequency
differential oscillator (LVDs or LVPECL) where external noise is
treated as a common-mode signal.

Regarding external EMI, put some metallic shielding around your
circuit.

Good luck, you will be fine (even better if you used Xilinx.  Just
kidding...)
Peter Alfke, Xilinx Applications
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

alessandro.strazzero@gmail.com wrote:
> Dear everybody,
>
> I have to design an ALTERA Cyclone FPGA based board which will be
> used in a rugged environment in terms of operating temperature
> (-40 to +85 =B0C) and strong EMI interference.
> I have to provide for the clock to the FPGA and I would like to use
> a 16 MHz oscillator which will be multiplicated by 8 by the Cyclone
> internal PLL in order to obtain a 128 MHz clock for the NIOS II
> processor.
>
> My doubts are the following:
> - is a good choise to connect directly the oscillator output to the
>   FPGA pin or for this kind of environment is suggested to build a
>   more reliable circuit around the oscillator ?
> - is a good choise using the internal PLL ?  Is it reliable in a
>   rugged environment ? (I have chosen an external low frequency
>   oscillator to reduce EMI emissions)
> - are there exist on the market any oscillator specifically designed
>   for rugged environment ?
>
> Hope someone of you have already experienced these kind of
> problematics in order to suggest me the best way to run.
>=20
> Best Regards
>=20
> /Alessandro Strazzero

Hi Alessandro,

> My doubts are the following:
> - is a good choise to connect directly the oscillator output to the
>   FPGA pin or for this kind of environment is suggested to build a
>   more reliable circuit around the oscillator ?

It would be best to have higher-frequency differential oscillator at,say, 32
or 64MHz, but basically, this should not be a huge problem.

> - is a good choise using the internal PLL ?  Is it reliable in a
>   rugged environment ? (I have chosen an external low frequency
>   oscillator to reduce EMI emissions)

A colleague of mine is using a 33MHz single-ended clock in combination with
the Cyclone PLL to control train engine inverters by directly controlling
the gates of a few _big_ IGBTs that steer about 1000A over 3200V. So far it
has been working flawlessly. The PLL even filters out spikes in the clock
signal to some extent.

The only thing that happened was during a torture test when he directly put
the PCB with the Cyclone on it in in a 4500V electric field, with about 1"
between cathode and anode where the PLL stopped running. On the other hand,
as you can imagine, lots of other electronics on the board went weird under
this condition as well, and this situation _should_ never occur in trains.
BTW: once the field was removed, the PLL started running again as if
nothing had happened.

Best regards,



Ben

alessandro.strazzero@gmail.com wrote:
> Dear everybody,
>
> I have to design an ALTERA Cyclone FPGA based board which will be
> used in a rugged environment in terms of operating temperature
> (-40 to +85 =B0C) and strong EMI interference.
> I have to provide for the clock to the FPGA and I would like to use
> a 16 MHz oscillator which will be multiplicated by 8 by the Cyclone
> internal PLL in order to obtain a 128 MHz clock for the NIOS II
> processor.
>
> My doubts are the following:
> - is a good choise to connect directly the oscillator output to the
>   FPGA pin or for this kind of environment is suggested to build a
>   more reliable circuit around the oscillator ?
> - is a good choise using the internal PLL ?  Is it reliable in a
>   rugged environment ? (I have chosen an external low frequency
>   oscillator to reduce EMI emissions)
> - are there exist on the market any oscillator specifically designed
>   for rugged environment ?
>
> Hope someone of you have already experienced these kind of
> problematics in order to suggest me the best way to run.
>
> Best Regards
>
> /Alessandro Strazzero

I think the idea of using PLL to reduce EMI may not work to your
advantage.
Externally induced noise can add to the jitter at the input pin of the
FPGA in a single-ended implementation (most low-frequency oscillators
are single ended and have relatively slow rise and fall times).  If you
can find a 128 MHz oscillator meeting the environmental requirements
and
LVDS or PECL output, you'll get lower EMI (due to differential drive)
and reduced jitter.

Check out offerings by Suntsu at:

http://www.suntsuinc.com

Including 2.5V LVDS at up to 200 MHz and -40 to +85 temp.

Dear everybody,

I have to design an ALTERA Cyclone FPGA based board which will be
used in a rugged environment in terms of operating temperature
(-40 to +85 =B0C) and strong EMI interference.
I have to provide for the clock to the FPGA and I would like to use
a 16 MHz oscillator which will be multiplicated by 8 by the Cyclone
internal PLL in order to obtain a 128 MHz clock for the NIOS II
processor.

My doubts are the following:
- is a good choise to connect directly the oscillator output to the
  FPGA pin or for this kind of environment is suggested to build a
  more reliable circuit around the oscillator ?
- is a good choise using the internal PLL ?  Is it reliable in a
  rugged environment ? (I have chosen an external low frequency
  oscillator to reduce EMI emissions)
- are there exist on the market any oscillator specifically designed
  for rugged environment ?

Hope someone of you have already experienced these kind of
problematics in order to suggest me the best way to run.

Best Regards

/Alessandro Strazzero