Hi Paul,

I ran this past one of the development kit people.  He can't definitively 
answer your questions without seeing your design, but his best guesses at 
what might be going on are below.  If you send your design to me I'll get 
him to take a look at it, and hopefully he could get you a more definitive 
answer.

Q - How do you decide by how much to phase shift the clock?

A - At 100Mhz no phase shift is needed on the clock. I can't think of any 
reason why a phase shift would be needed at 80 MHz either, and we did run 
some initial designs on this board at 80 MHz with no phase shift on the 
clock, and they worked.  I suspect this phase shift is covering a problem 
with how the project is set up. (Also refer to the answer to question 2 --  
perhaps that is related)

Q - It appears that my data is inverted, does anyone know if the ADC's on 
this board are active high or active low?

A - Two things to check

1) Where is the signal that you are feeding into the ADC's coming from? If 
looped back on the board like in the reference designs make sure the DAC's 
are pinned out correctly. The Data sheet on the DAC is confusing in that 
they pin the chip out to be Bit 1 - 14 which is how they are denoted in the 
schematic but in reality bit 1 is data 13 MSB and bit 14 is data 0 LSB. 
There is a note describing this on page 24 of the board data sheet.

2) The second thing to check is how you are interpreting your data. The ADC 
is set to output the data in 2's complement so make sure you are evaluating 
it as such.

Regards,

Vaughn
Altera
[v b e t z (at) altera.com]

"Paul Solomon" <psolomon@tpg.com.au> wrote in message 
news:430d5265@dnews.tpgi.com.au...
> Hello,
>
> I recentally purchased a Stratix II (60) DSP Dev Board (from Altera) and I 
> have been having a bit of trouble getting the ADC to work correctly and I 
> was wondering is there was anyone therer that had experience with this 
> board.
>
> I am able to get it to work when the clk is set to 100MHZ, but is I use a 
> PLL to run the clk at say 80MHz then the data that I read from the ADC 
> (also clocked at 80MHz from the same PLL output) is not clean. i.e. it is 
> similar to the signal I would expect however it has spikes in it 
> everywhere. I assume this is a clock skew issue or something like that. I 
> have found that if I use a seperate PLL output to drive the ADC clk then I 
> apply a 180 degree phase shift to that output then my data looks clean.
>
> So the questions I have are:
>
> 1) It would appear that you need to apply a phase shift on the adc clock 
> output to account for clock skew (or for some other reason). How do you 
> decide by how much to phase shift the clock? I chose 180 degrees at random 
> and it seems to work, however I am concerned that this was not a very 
> academic approach and I could be near a threshold of working / not 
> working.
>
> 2) It appears that my data is inverted, does anyone know if the ADC's on 
> this board are active high or active low? I had assumed active high as 
> there is no _n suffix next to the pin name, but my data does appear to be 
> upside down.
>
> Regards
>
> Paul Solomon
>
>
> 

Hello,

I recentally purchased a Stratix II (60) DSP Dev Board (from Altera) and I 
have been having a bit of trouble getting the ADC to work correctly and I 
was wondering is there was anyone therer that had experience with this 
board.

I am able to get it to work when the clk is set to 100MHZ, but is I use a 
PLL to run the clk at say 80MHz then the data that I read from the ADC (also 
clocked at 80MHz from the same PLL output) is not clean. i.e. it is similar 
to the signal I would expect however it has spikes in it everywhere. I 
assume this is a clock skew issue or something like that. I have found that 
if I use a seperate PLL output to drive the ADC clk then I apply a 180 
degree phase shift to that output then my data looks clean.

So the questions I have are:

1) It would appear that you need to apply a phase shift on the adc clock 
output to account for clock skew (or for some other reason). How do you 
decide by how much to phase shift the clock? I chose 180 degrees at random 
and it seems to work, however I am concerned that this was not a very 
academic approach and I could be near a threshold of working / not working.

2) It appears that my data is inverted, does anyone know if the ADC's on 
this board are active high or active low? I had assumed active high as there 
is no _n suffix next to the pin name, but my data does appear to be upside 
down.

Regards

Paul Solomon