Hallo,
I'm simulating a peripheral into modelsim.
I have watched some differences between: behavioral, post-translate, 
post-map, post-place simulations.

Using post-place simulation, the peripheral works well into modelsim. 
Instead, if I use post-map, modelsim shows some warnings like this:

#    Time: 299133929 ps  Iteration: 7  Instance: 
/wave/uut/adc_ram_addr_write_0_1_399
# ** Warning: /X_LATCHE HOLD  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.381 ns; Observed := 0 ns; At : 299133.929 ns

Then into behavioral simulation some signal are not initialized, even if I 
do it in vhdl file.

Why my system works well into a more real simulation?

I think it should be the opposite. It should works well into behavioral, and 
less well into post-place...

Many Thanks
Marco