mk wrote:
> actually 574 is not a latch but a posedge DFF with tri-state outputs

Oh, so it is. The difference being that the latch's Qout follows Din while EN 
is high, and the flipflop only latches data in when EN performs a L/H transition.

The things you only notice when you read the truth tables. I'm working from 
the TI "Digital Logic Pocket Data Book" here :)

I've been trying to model the whole lot in one file - never thought of 
modelling the DFFs and buffers separately... I've added the t74574 model to my 
code library - thanks for that.

Thanks,
-- 
Phil.                                | Acorn RiscPC600 SA220 64MB+6GB 100baseT
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On Sat, 03 Sep 2005 19:58:18 +0100, Philip Pemberton
<philpem@despammed.com> wrote:

>Hi,
>   I'm trying to reimplement the design at 
><http://themotionstore.com/leeedavison/6502/ide/index.html> in Verilog, 
>targetting a Xilinx CPLD. Problem is, I've got all the GAL equations 
>translated, but I can't work out how to handle the latches and buffers. Why am 
>I doing this? Because I'm out of 74LS chips and all my suppliers are closed 
>until Monday...
>
>   Basically, when /LDW goes active, the top-right '574 latches in the data on 
>D[0..7]. When /UDW goes active, the bottom-right '244 passes the data on 
>D[0..7] straight onto ID[8..15] and the top-right '574's output is enabled.
>   Reading is fairly simple too - /LDR goes active, the bottom-left '574 
>latches ID[8..15] and the top-left '245 passes the data on ID[0..7] onto 
>D[0..7]. When /UDR goes active, the '244 is inactive and the '574's output 
>gets enabled (ID[8..15] data gets popped onto the D[0..7] bus). Pretty simple 
>on paper.
>
>   How would you go about modelling this circuit in Verilog? Can anyone offer 
>me some hints or suggestions?
>
>Thanks,

actually 574 is not a latch but a posedge DFF with tri-state outputs
so you can model it as :

module t74574(CK, OEB, D, Q);
input CK, OEB;
input [7:0] D;
output [7:0] Q;

reg [7:0] Qi;

always @(posedge CK)
	Qi[7:0] <= D[7:0];

assign Q = OEB ? 8'hz : Qi;

endmodule

of course you have make sure that the pins of the CPLD are tristated
and not internal signals so the OEB should control pins of the CPLD.

Hi,
   I'm trying to reimplement the design at 
<http://themotionstore.com/leeedavison/6502/ide/index.html> in Verilog, 
targetting a Xilinx CPLD. Problem is, I've got all the GAL equations 
translated, but I can't work out how to handle the latches and buffers. Why am 
I doing this? Because I'm out of 74LS chips and all my suppliers are closed 
until Monday...

   Basically, when /LDW goes active, the top-right '574 latches in the data on 
D[0..7]. When /UDW goes active, the bottom-right '244 passes the data on 
D[0..7] straight onto ID[8..15] and the top-right '574's output is enabled.
   Reading is fairly simple too - /LDR goes active, the bottom-left '574 
latches ID[8..15] and the top-left '245 passes the data on ID[0..7] onto 
D[0..7]. When /UDR goes active, the '244 is inactive and the '574's output 
gets enabled (ID[8..15] data gets popped onto the D[0..7] bus). Pretty simple 
on paper.

   How would you go about modelling this circuit in Verilog? Can anyone offer 
me some hints or suggestions?

Thanks,
-- 
Phil.                                | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem@despammed.com (valid address)| Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/            | Panasonic CF-25 Mk.2 Toughbook
No software patents!          <http://www.eff.org/> /  <http://www.ffii.org/>