John,

Youa re absolutely right!  I failed to mention that you should always use the DDR FF for clock
forwarding, as it has the best timing performance.  Good catch.

Austin

John Providenza wrote:

> You may also want to use the DDR output flops in the IOB to
> output the clock rather than running them straight through
> a simple output buffer.  This keeps the clocks on dedicated
> clock lines and eliminates a bunch of skew.  There are several
> app-notes that show this, look at some of the DDR memory ones
> for examples.
>
> Here's code a used to drive a clock out to some synchronous SRAM.
> Note by swapping the D0 and D1 values you can invert the clock.
>
> // infer a DDR type I/O cell for low clock skew
> FDDRRSE uddr_clk(
>         .Q              (sram_clk),
>         .C0             (g_sr_clk),
>         .C1             (~g_sr_clk),
>         .CE             (1'b1),
>         .D0             (1'b1),
>         .D1             (1'b0),
>         .R              (1'b0),
>         .S              (1'b0)
> );
>
> John Providenza
>
> Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F8C4846.62042276@xilinx.com>...
> > Markus,
> >
> > Keep the OBUFs to the right or left sides, and near the center of the parts
> > (least H Clock Tree skew from IOB to IOB <<50 ps).
> >
> > Worst is to have them in the center of the top or bottom, and go to the
> > extreme right or left corners (~500 to 600 ps in 2VP100 skew).
> >
> > You can infer the skew on the hclck tree by examining delays in FPGA editor.
> >
> > Austin
> >
> > Markus Meng wrote:
> >
> > > Hi all,
> > >
> > > a simple question:
> > >
> > > We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but
> > > only ne feedback signal - of course. What is the best way to minimize the
> > > delay difference between the OBUF's?
> > >
> > > Any help would be appreciated.
> > >
> > > Markus

You may also want to use the DDR output flops in the IOB to
output the clock rather than running them straight through
a simple output buffer.  This keeps the clocks on dedicated
clock lines and eliminates a bunch of skew.  There are several
app-notes that show this, look at some of the DDR memory ones
for examples.

Here's code a used to drive a clock out to some synchronous SRAM.
Note by swapping the D0 and D1 values you can invert the clock.

// infer a DDR type I/O cell for low clock skew
FDDRRSE uddr_clk(
        .Q              (sram_clk),
        .C0             (g_sr_clk),
        .C1             (~g_sr_clk),
        .CE             (1'b1),
        .D0             (1'b1),
        .D1             (1'b0),
        .R              (1'b0),
        .S              (1'b0)
);



John Providenza


Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F8C4846.62042276@xilinx.com>...
> Markus,
> 
> Keep the OBUFs to the right or left sides, and near the center of the parts
> (least H Clock Tree skew from IOB to IOB <<50 ps).
> 
> Worst is to have them in the center of the top or bottom, and go to the
> extreme right or left corners (~500 to 600 ps in 2VP100 skew).
> 
> You can infer the skew on the hclck tree by examining delays in FPGA editor.
> 
> Austin
> 
> Markus Meng wrote:
> 
> > Hi all,
> >
> > a simple question:
> >
> > We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but
> > only ne feedback signal - of course. What is the best way to minimize the
> > delay difference between the OBUF's?
> >
> > Any help would be appreciated.
> >
> > Markus

Markus,

Keep the OBUFs to the right or left sides, and near the center of the parts
(least H Clock Tree skew from IOB to IOB <<50 ps).

Worst is to have them in the center of the top or bottom, and go to the
extreme right or left corners (~500 to 600 ps in 2VP100 skew).

You can infer the skew on the hclck tree by examining delays in FPGA editor.

Austin

Markus Meng wrote:

> Hi all,
>
> a simple question:
>
> We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but
> only ne feedback signal - of course. What is the best way to minimize the
> delay difference between the OBUF's?
>
> Any help would be appreciated.
>
> Markus

Hi all,

a simple question:

We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but
only ne feedback signal - of course. What is the best way to minimize the
delay difference between the OBUF's?

Any help would be appreciated.

Markus