pingboypulsar@hotmail.com wrote:
> thanks for that info.
> 
> So what is the best approach to learning how to do this?
> 
> Is it possible to elaborate a bit more on this "..so 2Gsps@8bits
> fans-out to 500Msps@32bits, where it can (just) feed into a FPGA..."

It's outside your Sensor reference area, but I included it as a limiting 
case, as an example. You can get ADCs ($$) that have 2 G samples/second,
and that is above FPGA abilties - but FPGAs have lots of pins, so the
solution is to create a wider, slower datapath out of the ADCs.
[the opposite of a SPI interface, if you like ]

<paste>
> I wish to be able to connect industrial sensor(s) to an adc, and 
> then acquire the value to the fpga for further processing. Maybe its 
> better to use an asic or something else for interfacing an adc. I 
> need to find out these things.

Physical connection is simple. 'Further processing' sounds like some
software, ie a SoftCPU.
There are truckloads of examples, of ADC <-> uC connections, and the
software needed to initialise the registers in the ADC, and then
pump the data out. That software is portable to your FPGA CPU.
  You have chosen an ADC partnumber, and FPGA SoftCPU ?

-jg

pingboypulsar<spamoff>@hotmail.com wrote:
> thanks for that info.
> 
> So what is the best approach to learning how to do this?
> 
> Is it possible to elaborate a bit more on this "..so 2Gsps@8bits
> fans-out to 500Msps@32bits, where it can (just) feed into a FPGA..."
> 
> Cheers!

I think you'll find that everyone is directing you to information on 
interfacing an FPGA to a separate ADC.  It is very hard, and not worth 
the effort to create a high performance ADC using the FPGA fabric. 
Instead using an external ADC is the best option.  If you really need an 
ADC integrated into some IC with extra logic, you'd have to look into 
utilising an ASIC.  Though there might be an FPGA out there with a 
custom ADC block integrated into it, it's not the norm however.



Bevan

thanks for that info.

So what is the best approach to learning how to do this?

Is it possible to elaborate a bit more on this "..so 2Gsps@8bits
fans-out to 500Msps@32bits, where it can (just) feed into a FPGA..."

Cheers!
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