Thanks everyone for the help!
I'll let you know when I get something going =)
Ben
"Antti Lukats" <antti@openchip.org> wrote in message 
news:dju0f3$gg9$1@online.de...
> "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> 
> schrieb im Newsbeitrag news:djkmeg$mdo$1@sunnews.cern.ch...
>>I know this isn't exactly comp.arch.cpld...
>>
>> does anyone know of a COTS solution for programming a (Xilinx) CPLD 
>> without using PC + Windows + Impact etc etc. (a stand alone chunk of 
>> hardware with a way for me to give it a set of bit files and a Program 
>> button would be nice)
>
> small uclinux modules sell for less than 100EUR.
> it takes a few hours to get XSVFplayer to work there.
> I use it in desing to program the XC9572XL, the mdoule we used was from 
> www.dilnetpc.com coldfire based,
> but the production has not changed to use small fpga linux modules 
> (microblaze uclinux)
> www.hydraxc.com
>
> antti
>

My intent was not to offend but merely to inform.  You indicated that 
you had a solution for the CoolRunner devices but he stated that he had 
used a 9500 device.  Since the programming operation of these devices 
are radically different and you made no indication of having a more 
general purpose solution I thought I would raise the issue.  I am sorry 
if you found that insulting in any way. Please accept my apologies.

dp wrote:
>>What you have the CoolRunner will not work for the xc9500 family because
>>the configuration algorithms are radically different.
> 
> 
> Having written the tools from scratch starting with
> the logic compiler and ending with the JTAG
> access hardware & software, thus my design chain being 100%
> self supplied - I would have thought I knew that.
>  I wonder based on what experience you thought
> I did not know.
> I offered the guy my help simply because I do have
> knowledge way above average on the subject and I might be of
> some help at some stage - he would probably know if and
> when.
> 
> Dimiter
> 
> ------------------------------------------------------
> Dimiter Popoff               Transgalactic Instruments
> 
> http://www.tgi-sci.com
> ------------------------------------------------------
>

"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> 
schrieb im Newsbeitrag news:djkmeg$mdo$1@sunnews.cern.ch...
>I know this isn't exactly comp.arch.cpld...
>
> does anyone know of a COTS solution for programming a (Xilinx) CPLD 
> without using PC + Windows + Impact etc etc. (a stand alone chunk of 
> hardware with a way for me to give it a set of bit files and a Program 
> button would be nice)

small uclinux modules sell for less than 100EUR.
it takes a few hours to get XSVFplayer to work there.
I use it in desing to program the XC9572XL, the mdoule we used was from 
www.dilnetpc.com coldfire based,
but the production has not changed to use small fpga linux modules 
(microblaze uclinux)
www.hydraxc.com

antti

>What you have the CoolRunner will not work for the xc9500 family because
>the configuration algorithms are radically different.

Having written the tools from scratch starting with
the logic compiler and ending with the JTAG
access hardware & software, thus my design chain being 100%
self supplied - I would have thought I knew that.
 I wonder based on what experience you thought
I did not know.
I offered the guy my help simply because I do have
knowledge way above average on the subject and I might be of
some help at some stage - he would probably know if and
when.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

What you have the CoolRunner will not work for the xc9500 family because 
the configuration algorithms are radically different.

dp wrote:
> Benjamin,
> I have made/written tools to program some of the Coolrunner
> CPLDs, I have them running on either a CPU32 (683xx) or
> PPC based system. Please feel free to contact me directly
> if you think I might be of some help.
> 
> Regards,
> Dimiter
> 
> ------------------------------------------------------
> Dimiter Popoff               Transgalactic Instruments
> 
> http://www.tgi-sci.com
> ------------------------------------------------------
>

Benjamin,
I have made/written tools to program some of the Coolrunner
CPLDs, I have them running on either a CPU32 (683xx) or
PPC based system. Please feel free to contact me directly
if you think I might be of some help.

Regards,
Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

Ah, the board is already in the pre-series stage,  there are a couple of 
reasons why we chose a 9500 CPLD (yes I know, very old!)...
5V internal = only one PSU needed & whole board at 5V which is excellent for 
reliability,
our radiation campaigns showed that it's highly immune to soft-errors (TID 
was much more effective),
It's active almost as soon as it is powered up whereas FPGAs must wait 
whilst they are being programmed. And we simply don't need the complexity of 
an FPGA.
Don't get me wrong, we use all manner of Xilinx stuff in the lastest project 
(95288 95144XL XC2C128 XC2S400 XC3S1000) just depends on the exact nature of 
the application.
I think I might investigate the Microprocessor alternative, just then have 
to figure out how to get the .bit file into some flash near the 
microprocessor in a reliable and easy manner.
Ah well.
Ben

"Neil Glenn Jacobson" <n.e.i.l.j.a.c.o.b.s.o.n@x.i.l.i.n.x.c.o.m> wrote in 
message news:djrarf$a2r1@cliff.xsj.xilinx.com...
> OK. Fair enough.  And you could use SystemACE to do all that except for 
> programming the CPLD.  Why use a CPLD and not just a small, cheap FPGA 
> like a Spartan3 or a variant?
>
>
> Benjamin Todd wrote:
>>>As also indicated, an interesting question to ask is why do you want to 
>>>configure your CPLD every time you power up?  Is your design pattern 
>>>changing all the time?  Is this some sort of demo board?
>>
>>
>> Not exactly, maybe i'm being a little ambitious...
>>
>> I'm just doing some research into making a test apparatus for some 
>> designs using various CPLDs.  The idea was to make a discrete piece of 
>> hardware that the UUT would be plugged into, and then a little report 
>> saying whether it passes or fails - this needs to be rugged, and 
>> industrialised.
>>
>> Using boundary scan I can only verify about half the board, and the less 
>> critical half at that, so i'm wondering whether I could use one bit file 
>> to run a sequence of test vectors in conjunction with the external 
>> tester, and then once all the interconnects are established as correct, 
>> load the proper bit file.
>>
>> I guess you're wondering why I don't just go for a PC running impact... 
>> well i'm trying to avoid having to maintain a PC with the manufacturer, 
>> including the OS, the test software etc etc.
>>
>> Ben
>>
>>
>>
>>

OK. Fair enough.  And you could use SystemACE to do all that except for 
programming the CPLD.  Why use a CPLD and not just a small, cheap FPGA 
like a Spartan3 or a variant?


Benjamin Todd wrote:
>>As also indicated, an interesting question to ask is why do you want to 
>>configure your CPLD every time you power up?  Is your design pattern 
>>changing all the time?  Is this some sort of demo board?
> 
> 
> Not exactly, maybe i'm being a little ambitious...
> 
> I'm just doing some research into making a test apparatus for some designs 
> using various CPLDs.  The idea was to make a discrete piece of hardware that 
> the UUT would be plugged into, and then a little report saying whether it 
> passes or fails - this needs to be rugged, and industrialised.
> 
> Using boundary scan I can only verify about half the board, and the less 
> critical half at that, so i'm wondering whether I could use one bit file to 
> run a sequence of test vectors in conjunction with the external tester, and 
> then once all the interconnects are established as correct, load the proper 
> bit file.
> 
> I guess you're wondering why I don't just go for a PC running impact... well 
> i'm trying to avoid having to maintain a PC with the manufacturer, including 
> the OS, the test software etc etc.
> 
> Ben
> 
> 
> 
> 
>

> As also indicated, an interesting question to ask is why do you want to 
> configure your CPLD every time you power up?  Is your design pattern 
> changing all the time?  Is this some sort of demo board?

Not exactly, maybe i'm being a little ambitious...

I'm just doing some research into making a test apparatus for some designs 
using various CPLDs.  The idea was to make a discrete piece of hardware that 
the UUT would be plugged into, and then a little report saying whether it 
passes or fails - this needs to be rugged, and industrialised.

Using boundary scan I can only verify about half the board, and the less 
critical half at that, so i'm wondering whether I could use one bit file to 
run a sequence of test vectors in conjunction with the external tester, and 
then once all the interconnects are established as correct, load the proper 
bit file.

I guess you're wondering why I don't just go for a PC running impact... well 
i'm trying to avoid having to maintain a PC with the manufacturer, including 
the OS, the test software etc etc.

Ben