"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag 
news:dki76s$cb1$1@online.de...
> Why Spartan-3e is the best
> ==================
>  Antti Lukats
>  4.Nov 2005
>
> [lot's of indispensable 3e advantages snipped]
>
> 6) There are possible some other nice new features
> I have not discovered yet :)

Yes, you forgot to mention the extra fun you may have with the DCM / DFS 
 >90MHz && <220MHz.

Raymund Hofmann 

I wrote:
> The problem is that you don't save any significant cost by having the
> same size package with fewer balls or pins.  So if the die size requires
> a package 20mm on a side, it may as well have more than 350 balls, even
> if some customers don't end up using all of them.

Tobias Weingartner wrote:
> There is a cost associated with me trying to acquire the resources and
> planning necessary to have a 1000+ pin FPGA mounted, routed and fed.  On
> the other hand, 144 pins, or even 208 pins in a quad flat pack is pretty
> much doable...

Sure, but if the part doesn't fit in the die cavity of the package, it
ain't gonna happen.

"Bevan Weiss" <kaizen__@NOSPAM.hotmail.com> wrote in message 
news:uFacf.1820$xD6.102150@news.xtra.co.nz...
> langwadt@ieee.org wrote:
>> Ray Andraka wrote:
>>> Tobias Weingartner wrote:
>>>
>>>> I realize that there are people out there that need the 1000+ pin 
>>>> packages
>>>> that large-scale FPGAs offer... but I do wish that 2-5 million "gate" 
>>>> FPGAs
>>>> would come in VQ100/144 packages.  Personally, I'd love to have the 
>>>> capacity,
>>>> but I really dont need (or want) the complexity and raw bandwidth of 
>>>> having
>>>> to deal with several hundred (or a thousand) pins...
>>>>
>>>>
>>> Unfortunately, the size of the cavity in those small packages is far too
>>> small to fit the die for the high density parts, and even if it did fit,
>>> you may have power dissipation issues as well.
>>>
>>> --
>>> --Ray Andraka, P.E.
>>
>> any idea how big the dies are?, what will fit in a vq100, the only
>> thing I could find on the web was  something like 3x3mm sounds small
>> for a 10x10 package?
>>
>> -Lasse
>
> That sounds about right to me.
> You've got to remember there's a tolerance on the die placement, so the 
> interior die 'room' needs to be larger, then you've got the anchor space 
> for the pins themselves and then the added space for the wirebonds.
>
> BGAs can accommodate much larger dies given equivalent sizing to QFP etc 
> etc.  They don't require any room for wirebonds in almost all cases.

Guys,
Here's the problem. These days all the parts are made on 90-130 nm 
processes. This means that the transistors switch very quickly. They also 
have lower power supply voltages, lowering the noise threshold. This means 
that even if the dice fitted the lead frame of a PQFP, the SI would be 
awful, probably such that the thing wouldn't work. There'd be bloody great 
inductors between the board ground and the die ground. The frequency isn't 
the limiting thing, it's the rise time. So, saying you're only gonna drive 
the outputs at 20 Mbps, doesn't fix the problem of sub ns rise/fall time. 
You could have small packages like Amkor's micro-lead-frame (MLF) QFN stuff 
with exposed paddles, but I guess if you don't like BGA, you're not gonna 
like that either.
Cheers, Syms. 

langwadt@ieee.org wrote:
> Ray Andraka wrote:
>> Tobias Weingartner wrote:
>>
>>> In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote:
>>>
>>>
>>>> as example VQ100 is really nice package very thin, so largest LUTs you get
>>>> in VQ100 is S3e. etc..
>>>>
>>>>
>>> I realize that there are people out there that need the 1000+ pin packages
>>> that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs
>>> would come in VQ100/144 packages.  Personally, I'd love to have the capacity,
>>> but I really dont need (or want) the complexity and raw bandwidth of having
>>> to deal with several hundred (or a thousand) pins...
>>>
>>>
>>>
>> Unfortunately, the size of the cavity in those small packages is far too
>> small to fit the die for the high density parts, and even if it did fit,
>> you may have power dissipation issues as well.
>>
>> --
>> --Ray Andraka, P.E.
> 
> any idea how big the dies are?, what will fit in a vq100, the only
> thing I could find on the web was  something like 3x3mm sounds small
> for a 10x10 package?
> 
> -Lasse

That sounds about right to me.
You've got to remember there's a tolerance on the die placement, so the 
interior die 'room' needs to be larger, then you've got the anchor space 
for the pins themselves and then the added space for the wirebonds.

BGAs can accommodate much larger dies given equivalent sizing to QFP etc 
etc.  They don't require any room for wirebonds in almost all cases.

Ray Andraka wrote:
> Tobias Weingartner wrote:
>
> >In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote:
> >
> >
> >>as example VQ100 is really nice package very thin, so largest LUTs you get
> >>in VQ100 is S3e. etc..
> >>
> >>
> >
> >I realize that there are people out there that need the 1000+ pin packages
> >that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs
> >would come in VQ100/144 packages.  Personally, I'd love to have the capacity,
> >but I really dont need (or want) the complexity and raw bandwidth of having
> >to deal with several hundred (or a thousand) pins...
> >
> >
> >
> Unfortunately, the size of the cavity in those small packages is far too
> small to fit the die for the high density parts, and even if it did fit,
> you may have power dissipation issues as well.
>
> --
> --Ray Andraka, P.E.

any idea how big the dies are?, what will fit in a vq100, the only
thing I could find on the web was  something like 3x3mm sounds small
for a 10x10 package?

-Lasse

In article <qhhdao850d.fsf@ruckus.brouhaha.com>, Eric Smith wrote:
> 
> The problem is that you don't save any significant cost by having the
> same size package with fewer balls or pins.  So if the die size requires
> a package 20mm on a side, it may as well have more than 350 balls, even
> if some customers don't end up using all of them.

There is a cost associated with me trying to acquire the resources and
planning necessary to have a 1000+ pin FPGA mounted, routed and fed.  On
the other hand, 144 pins, or even 208 pins in a quad flat pack is pretty
much doable...

Now, my naivitee(sp?) may show here, it may be that the power requirements
for feeding such a beast can simply not be reliably met by the (T)QFP type
of package...

-- 
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

In article <xVPbf.1529$xD6.92174@news.xtra.co.nz>, Bevan Weiss wrote:
> 
> Just doesn't work that way unfortunately.  The large fabric requires a 
> large chip package to contain it.  If you were to reduce the number of 
> pin outs, the it would actually require an even larger chip package, as 
> you would now have to add additional multiplexers etc to control the 
> routing to the pins.

You've got an FPGA to help you route stuff... :)

-- 
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

> [largest fabric in small package among fpga families]
Thanks Jim and Antti for clearing that up.

-- Jecel

Tobias Weingartner wrote:

>In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote:
>  
>
>>as example VQ100 is really nice package very thin, so largest LUTs you get 
>>in VQ100 is S3e. etc..
>>    
>>
>
>I realize that there are people out there that need the 1000+ pin packages
>that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs
>would come in VQ100/144 packages.  Personally, I'd love to have the capacity,
>but I really dont need (or want) the complexity and raw bandwidth of having
>to deal with several hundred (or a thousand) pins...
>
>  
>
Unfortunately, the size of the cavity in those small packages is far too 
small to fit the die for the high density parts, and even if it did fit, 
you may have power dissipation issues as well.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Bevan Weiss wrote:
> Just doesn't work that way unfortunately.  The large fabric requires a
> large chip package to contain it.  If you were to reduce the number of
> pin outs, the it would actually require an even larger chip package,
> as you would now have to add additional multiplexers etc to control
> the routing to the pins.

No, it wouldn't need any extra multiplexers.  They would just not bond
out as many of the pads to pins.  They already do that to offer several
package options for each FPGA.

The problem is that you don't save any significant cost by having the
same size package with fewer balls or pins.  So if the die size requires
a package 20mm on a side, it may as well have more than 350 balls, even
if some customers don't end up using all of them.