Seemes strange to me.
The UART supplied in SOPC builder, under Communication, on my system
can be configured for up to 115200bps. It might not have a FIFO, but it
supports streaming, so you should be able to connect it to your own
FIFO.
Reply by Mark McDougall●November 17, 20052005-11-17
lesnleung@gmail.com wrote:
> We are working on a proect using NIOS which needs to talk to the PC
> Via a serial port, However we found that the core supplied by AILTERA
> seems to work at slow speed only even the core is runing at 50mhz, it
> seems that it cannot run faster than 2400baud, Any body has silmiar
> problems? We are trying a UART with FIFO but still struggling with
> it.
You could try using the opencores 16550. Having a wishbone interface it
wraps nicely into a SOPC component...
Regards,
Mark
Reply by Tim Wescott●November 17, 20052005-11-17
lesnleung@gmail.com wrote:
> We are working on a proect using NIOS which needs to talk to the PC Via
> a serial port, However we found that the core supplied by AILTERA seems
> to work at slow speed only even the core is runing at 50mhz, it seems
> that it cannot run faster than 2400baud, Any body has silmiar problems?
> We are trying a UART with FIFO but still struggling with it.
>
> Any ideas/ suggestion?
>
UARTs are easy. These work at 19.2k on a Spartan 2e clocked at 24MHz,
IIRC. If you want FIFOs and all that fancy stuff you'll have to add
them -- these are just basic UARTs that expect to be backed up by logic
that's just sitting around waiting for a job to do.
I'm a beginner at verilog design; apparently that means that I had
trouble remembering how to make comments...
/**********************************************************************
asyncSer.v
Description:
Various handy utility modules.
**********************************************************************/
`define IDLE_BIT 0
`define START_BIT 1
`define DATA_BIT 2
`define STOP_BIT 3
module asyncTx(clock, reset, data, write, txd, rts, empty);
parameter baudDiv = 11'd1280;
input clock;
input reset;
input [7:0] data;
input write;
output reg txd;
output reg rts;
output reg empty;
reg [7:0] shift;
reg [2:0] count;
reg [1:0] state;
reg [10:0] baud;
always @ (state) empty = state == `IDLE_BIT;
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
rts <= 0;
txd <= 1;
empty <= 1;
state <= `IDLE_BIT;
baud <= baudDiv - 1;
end
else
begin
if (state != `IDLE_BIT) baud <= baud ? baud - 1 : baudDiv - 1;
case (state)
`IDLE_BIT:
if (write)
begin
state <= `START_BIT;
shift <= data;
count <= 7;
end
`START_BIT:
if (!baud)
begin
txd <= 0;
state <= `DATA_BIT;
end
`DATA_BIT:
if (!baud)
begin
txd <= shift[0];
shift <= {1'bx, shift[7:1]};
count <= count - 1;
if (!count)
begin
state <= `STOP_BIT;
end
end
`STOP_BIT:
if (!baud)
begin
txd <= 1;
state <= `IDLE_BIT;
end
endcase
end
end
endmodule
module asyncRx(clock, reset, rxd, read, data, frameError, overflow, ready);
parameter baudDiv = 7'd80;
input clock;
input reset;
input rxd;
input read;
output reg [7:0] data;
output reg frameError;
output reg overflow;
output wire ready;
reg intReady;
reg [2:0] rxdBuff; // shift register to prevent metastability
reg [2:0] count; // bit count (0-7)
reg [1:0] state; // receiver state
reg [6:0] baud; // baud rate * 16 register
reg [3:0] subBaud; // baud rate reg
wire rxdBit;
assign rxdBit = rxdBuff[2];
assign ready = intReady;
always @ (posedge reset or posedge clock)
if (reset)
begin
state <= `IDLE_BIT;
rxdBuff <= 0;
data <= 0;
count <= 7;
baud <= baudDiv - 1;
subBaud <= 15;
overflow <= 0;
intReady <= 0;
frameError <= 0;
end
else
begin
rxdBuff <= {rxdBuff[1:0], rxd}; // shift for metastability prevention
if (baud) baud <= baud - 1;
else
begin
baud <= baudDiv - 1;
if (state != `IDLE_BIT) subBaud <= subBaud - 1;
end
if (read && intReady)
begin
intReady <= 0;
frameError <= 0;
overflow <= 0;
end
case (state)
`IDLE_BIT:
if (!rxdBit)
begin
state <= `START_BIT;
subBaud <= 15;
end
`START_BIT:
begin
if (!baud && subBaud == 8)
begin
if (rxdBit)
begin
overflow <= intReady;
if (!intReady) intReady <= 1;
frameError <= 1;
state <= `IDLE_BIT;
end
end
if (!baud && subBaud == 0)
begin
state <= `DATA_BIT;
count <= 7;
end
end
`DATA_BIT:
begin
if (!baud && subBaud == 8)
begin
data <= {!rxdBit, data[7:1]};
end
if (!baud && subBaud == 0)
begin
if (count == 0)
begin
state <= `STOP_BIT;
end
count <= count - 1;
end
end
`STOP_BIT:
begin
if (!baud && subBaud == 8)
begin
if (!rxdBit)
begin
frameError <= 1;
state <= `IDLE_BIT;
end
overflow <= intReady;
if (!intReady) intReady <= 1;
end
if (!baud && subBaud == 0)
begin
state <= `IDLE_BIT;
end
end
endcase
end
endmodule
/**********************************************************************
$Log: asyncSer.v,v $
Revision 1.6 2005/02/15 18:52:26 Tim
Make transmission start immediately instead of on a bit boundary
Revision 1.5 2005/02/15 00:32:44 Tim
Add asynchronous receive capability
Revision 1.4 2004/11/30 22:51:58 Tim
Make baud rate a parameter
Revision 1.3 2004/10/19 20:51:36 Tim
Add a buffer empty indicator
Revision 1.2 2004/08/29 20:16:18 Tim
Fix some symbol incompatibility issues
Revision 1.1 2004/08/13 19:19:03 Tim
Initial revision
**********************************************************************/
/**********************************************************************
asyncSer_test.v
Description:
Test various handy utility modules.
**********************************************************************/
`timescale 1ns/100ps
module async_test_bench;
reg clock;
reg reset;
reg rxd;
reg read;
wire [7:0] data;
wire frameError, overflow, ready;
always begin
clock <= 0;
#20;
clock <= 1;
#20;
end
initial begin
$display("Starting simulation");
rxd <= 1;
reset <= 0;
#11;
reset <= 1;
#11;
reset <= 0;
// simulate a framing error in the start bit
#100
rxd <= 0;
#300
rxd <= 1;
// simulate a good byte
#50000
rxd <= 0;
#200000
rxd <= 1;
// simulate a framing error in the stop bit
#400000
rxd <= 0;
#550000
rxd <= 1;
end
asyncRx inPort(
.clock(clock),
.reset(reset),
.rxd(rxd),
.read(read),
.data(data),
.frameError(frameError),
.overflow(overflow),
.ready(ready)
);
always @ (posedge clock or posedge reset)
begin
if (reset) read <= 0;
else
begin
read <= ready && !read;
end
end
endmodule
/**********************************************************************
$Log: asyncSer_test.v,v $
Revision 1.1 2005/02/04 22:14:58 Tim
Initial revision
**********************************************************************/
##########################################################################
#
# async_test.do
#
# $Id: async_test.do,v 1.1 2005/02/07 18:50:14 Tim Exp $
# $Author: Tim $
# $Date: 2005/02/07 18:50:14 $
# $Name: $
# $Revision: 1.1 $
#
# Description:
#
# Modelsim script for async debugging
#
##########################################################################
vsim async_test_bench
restart -f
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /async_test_bench/clock
add wave -noupdate -format Logic /async_test_bench/reset
add wave -noupdate -format Logic /async_test_bench/rxd
add wave -noupdate -format Logic /async_test_bench/read
add wave -noupdate -format Logic /async_test_bench/data
add wave -noupdate -format Logic /async_test_bench/frameError
add wave -noupdate -format Logic /async_test_bench/overflow
add wave -noupdate -format Logic /async_test_bench/ready
add wave -noupdate -format Literal -radix hexadecimal
/async_test_bench/inPort/rxdBuff
add wave -noupdate -format Literal -radix hexadecimal
/async_test_bench/inPort/count
add wave -noupdate -format Literal -radix hexadecimal
/async_test_bench/inPort/state
add wave -noupdate -format Literal -radix hexadecimal
/async_test_bench/inPort/baud
add wave -noupdate -format Literal -radix hexadecimal
/async_test_bench/inPort/subBaud
run 5.0ms
##########################################################################
#
# $Log: async_test.do,v $
# Revision 1.1 2005/02/07 18:50:14 Tim
# Initial revision
#
# Revision 1.3 2004/12/23 19:24:03 Tim
# Make changes to match main-line async code
#
# Revision 1.2 2004/12/14 19:58:35 Tim
# test 8-bit output debug_av.v
#
# Revision 1.1 2004/12/14 17:35:58 Tim
# Initial revision
#
##########################################################################
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Reply by ●November 17, 20052005-11-17
We are working on a proect using NIOS which needs to talk to the PC Via
a serial port, However we found that the core supplied by AILTERA seems
to work at slow speed only even the core is runing at 50mhz, it seems
that it cannot run faster than 2400baud, Any body has silmiar problems?
We are trying a UART with FIFO but still struggling with it.
Any ideas/ suggestion?