Reply by Andrew Lohbihler●November 24, 20052005-11-24
"Brian Davis" <brimdavis@aol.com> wrote in message
news:1132660954.262101.295110@g14g2000cwa.googlegroups.com...
> Andrew Lohbihler wrote:
>>
>> I've been using the uart_tx and uart_rx core EDIF's provided
>> by Xilinx in xapp223
> <snip>
>>Does anyone know/have a free/$ replacement to these EDIF's
>> that work for the Virtex-4?
>>
>
> see Ken Chapman's old post pointing to the VHDL equivalent of the
> XAPP223 UARTS, which can be found in the Picoblaze sources:
> http://groups.google.com/group/comp.arch.fpga/msg/0d3017a2beb810fd
>
> Brian
>
Thanks to all!
i did find the source code in www.picoblaze.com as Ken Chapman's code. The
old EDIF's are not reproducable for the V4 because of the architecture
changes from V2 to V4. The souce code solves these issues.
-Andrew
Reply by Brian Davis●November 22, 20052005-11-22
Andrew Lohbihler wrote:
>
> I've been using the uart_tx and uart_rx core EDIF's provided
> by Xilinx in xapp223
<snip>
>Does anyone know/have a free/$ replacement to these EDIF's
> that work for the Virtex-4?
>
Did you try generating same for Virtex-4 in Xilinx CoreGen?
Reply by Andrew Lohbihler●November 22, 20052005-11-22
Hi,
I've been using the uart_tx and uart_rx core EDIF's provided by Xilinx in
xapp223. These are great for my Virtex-II development, and they obviously
don't work for the Virtex-4. I like the simplicity of these cores and want
to change as little of my old code as possible. Does anyone know/have a
free/$ replacement to these EDIF's that work for the Virtex-4?
-Andrew