Hi all,


is there a way to access the phase accumulator in Xilinx DDS 5.0?

(preferably from VHDL)



I'd like to determine the carrier phase between two modulated signals

by phaselocking an NCO on each one and then subtracting the phase accus.



Given that there is a great DDS already, I dislike reinventing it

just to tap an internal signal.



BTW the register interface is nice if I want to setup everything with a

microcontroller. But ---  in a pure hardware environment it is clumsy to

multiplex frequency word and phase modulation to a 32 bit data bus

+ address line + WE,   knowing the first thing to happen is that they will
be

demultiplexed again into different registers. In addition the update rates

are halved    and potentially simultaneous frequency/phase updates need to

be scheduled.

(Options for DDS 5.1???)



best regards, Gerhard