Yes, this will work fine (it is what I did in my project).  Be sure,
though, that you properly handle the PLL pins.  In my design, I tied
both GNDA_PLL pins to ground and the VCCA_PLL pint to 1.5V with a
.001uF capacitor.  I believe I got the pinning information from the
datasheet.

Just make sure that you tie the osc to one of the clock pins that drives 
into the global clock network.


"Binary" <binary.chen@gmail.com> wrote in message 
news:1135735920.634199.74660@g14g2000cwa.googlegroups.com...
> Hi all,
>
> I have a Altera Cyclone chip which is input by a 50MHz osc. I want to
> use this 50MHz clock directly without PLL. This means I just use a clk
> as input and assign the PIN GCLK to clk.
>
> Is it OK?
>
> Thanks in advance.
>
> ABAI
> 

No problem.. Using PLL is optional..
If you have a doubt yet, use PLL with 1x, 1 div. setting.
(P.S In subject.. with-> without.. Am I right?)

Hi all,

I have a Altera Cyclone chip which is input by a 50MHz osc. I want to
use this 50MHz clock directly without PLL. This means I just use a clk
as input and assign the PIN GCLK to clk.

Is it OK?

Thanks in advance.

ABAI