Monica,
you can avoid the delay by clocking everything with the fast clock, and
using a 1-of-8 Clock Enable for the slow circuitry. That keeps
everything in the same clock domain. The only drawback is the higher
power consumption due to the wide distribution of the fast clock.

If almost everything runs at the slower clock, then it might make sense
to analyze carefully whether you can tolerate the skew between the fast
and the slow clock. Yes, you would use the third bit of a synchronous
counter as the slower clock. Do not even think about a ripple-counter
:-(
Since your "high" clock frequency is only 40 MHz, you can also
camouflage the clock skew by using the "other" edge of the 40 MHz
clock...
Frohes Neues Jahr!
Peter Alfke

Peter Alfke wrote:

Hallo,

> Monica, the DCM is obviously not well suited to cope with drastic
> changes in its input frequency.
> I would just forget the DCM (in this application) and use three good
> old flip-flops to build a (synchronous) divide-by-eight circuit. All
> your problems are gone...  :-)
> Peter Alfke, Xilinx Applications

Do you mean to use a 3bit counter and connect the Most significant bit
to output clock?
But I fear there will be some delays between the master clock and
derived clock.
Wont we have problems when tranferring data from the derived clock
domain to master clock domain?

I am using DCM because it gives zero delay 1/8th Clock.

Kindly let me if I understood your suggestion correctly.

Thanking you,
Monica

Peter,

Yes, I agree!  If all we are doing is dividing by 8, then a DCM is 
definitely not required.

Thanks for observing the obvious.

"When you are a hammer, every problem looks like a nail."

Austin (ex DCM IC design team member)

Peter Alfke wrote:

> Monica, the DCM is obviously not well suited to cope with drastic
> changes in its input frequency.
> I would just forget the DCM (in this application) and use three good
> old flip-flops to build a (synchronous) divide-by-eight circuit. All
> your problems are gone...  :-)
> Peter Alfke, Xilinx Applications
>

Monica, the DCM is obviously not well suited to cope with drastic
changes in its input frequency.
I would just forget the DCM (in this application) and use three good
old flip-flops to build a (synchronous) divide-by-eight circuit. All
your problems are gone...  :-)
Peter Alfke, Xilinx Applications

If you have

clk_in -> DCM -> clk_out

with clk_out being 1/8th of the frequency of clk_in, you can add a
small logic block clocked from clk_in that samples clk_out 8 times,
then count the number of 1 to find out the duty cycle (or 16/24/32
times, juste to be sure) and if the duty changes too much, then that
means the DCM needs to be reset.

Monica,

Not sure you can deal with this problem.

If you have 8 MHz output, be sure you are not going below the min output 
frequency specification.  It would be safer to use CLKDV, and divide 
down to 8 MHz from a hiugher frequency (like a divide by 5 from 40 MHz).

Then, I would use two DCM's.

One DCM is used to monitor the quality, and is periodically reset so 
that it can be used as a monitor (checking that it is always able to 
re-lock properly).

The other DCM is used to provide the output.  If the monitor DCM 
indicates after a reset that its status is better (ie it is locked and 
OK), then that would tell you that it would would be useful to reset the 
DCM providing the output.

One can also have a difference detector from the output of the two DCMs. 
  If the reset and test DCM output is different from the operating DCM; 
that is also an indication that the input has drifted too far, and the 
operating DCM is lost.

Just a couple thoughts,

Austin

Monica wrote:

> Hallo,
> 
> Thank you very much for the suggestion.
> 
> If I understand the datasheet of the DCM correctly,status bits indicate
> the following things.
> 
> status[0] indicate if phase shifter has reached its maximum value
> status[1] indicate if CLKIN is present or not
> status[2] indicate CLKFX and CLKFX180 are present or not
>  and remaining status bits are reserved(invalid).
> 
> How can we determine whether DCM has locked or not using these status
> lines?Did I interpret the data sheet incorrectly?
> 
> yes I will reset the DCM if it can show that it is not locked.The
> problem is it is showing that it has locked but giving incorrect
> clock.if it can give an indication that it cannot lock or lock is
> lost,then I can reset the DCM.
> 
> Unfortunately system which changes the frequency cannot reset or give
> an indication to the FPGA.if we have to do it then we must redesign our
> hardware to give an addtional line from that system to the FPGA.We will
> do it only if nothing else can be done to solve the problem(because it
> costs heavily).
> 
> Kindly let me know how can i deal with this problem.
> 
> Thank you very much,
> Monica
>

Dear John Adair,

Thank you very much for the reply.I need an addtional lines to the FPGA
to indicate this frequency change.Time to fight with PCB engineer to
provide one additional line.

Thanks a lot,
Monica

Monica

The status lines may not be enough. Depending on what happens when you clock 
changes but you may get the "not present" showing long enough that you can 
register the event.

Other ways to detect clocks running fast or slow but usually you need some 
kind of reference clock to compare or run logic from. With the large step 
frequency you have it would be easy to detect. Either way you will need more 
than the DCM alone to get an indicator. I don't think Xilinx every envisaged 
coping with a dynamic clock input as you describe. DCMs tend to like nice 
stable clocks.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"Monica" <monica_dsz@yahoo.com> wrote in message 
news:1136387011.980099.285940@f14g2000cwb.googlegroups.com...
> Hallo,
>
> Thank you very much for the suggestion.
>
> If I understand the datasheet of the DCM correctly,status bits indicate
> the following things.
>
> status[0] indicate if phase shifter has reached its maximum value
> status[1] indicate if CLKIN is present or not
> status[2] indicate CLKFX and CLKFX180 are present or not
> and remaining status bits are reserved(invalid).
>
> How can we determine whether DCM has locked or not using these status
> lines?Did I interpret the data sheet incorrectly?
>
> yes I will reset the DCM if it can show that it is not locked.The
> problem is it is showing that it has locked but giving incorrect
> clock.if it can give an indication that it cannot lock or lock is
> lost,then I can reset the DCM.
>
> Unfortunately system which changes the frequency cannot reset or give
> an indication to the FPGA.if we have to do it then we must redesign our
> hardware to give an addtional line from that system to the FPGA.We will
> do it only if nothing else can be done to solve the problem(because it
> costs heavily).
>
> Kindly let me know how can i deal with this problem.
>
> Thank you very much,
> Monica
>

Hallo,

Thank you very much for the suggestion.

If I understand the datasheet of the DCM correctly,status bits indicate
the following things.

status[0] indicate if phase shifter has reached its maximum value
status[1] indicate if CLKIN is present or not
status[2] indicate CLKFX and CLKFX180 are present or not
 and remaining status bits are reserved(invalid).

How can we determine whether DCM has locked or not using these status
lines?Did I interpret the data sheet incorrectly?

yes I will reset the DCM if it can show that it is not locked.The
problem is it is showing that it has locked but giving incorrect
clock.if it can give an indication that it cannot lock or lock is
lost,then I can reset the DCM.

Unfortunately system which changes the frequency cannot reset or give
an indication to the FPGA.if we have to do it then we must redesign our
hardware to give an addtional line from that system to the FPGA.We will
do it only if nothing else can be done to solve the problem(because it
costs heavily).

Kindly let me know how can i deal with this problem.

Thank you very much,
Monica