On Sat, 07 Jan 2006 08:51:49 -0800, "Mike Treseler"
<mike_treseler@comcast.net> wrote:

>John Larkin wrote:
>
>> I don't have time to learn an HDL. I read the Xilinx book, draw
>> schematics (on paper!), and hand them to a minion to enter and
>> compile.
>
>Ah! The academic solution.
>Where have all the minions gone?
>Long time passing ...
>

When will they ever learn,

When will they ever learn?


John

Absolutely.

John Larkin wrote:

> I don't have time to learn an HDL. I read the Xilinx book, draw
> schematics (on paper!), and hand them to a minion to enter and
> compile.

Ah! The academic solution.
Where have all the minions gone?
Long time passing ...

    -- Mike Treseler

Altera
In the field of both user interface and functionlity.

I think you're wrong.

John Larkin wrote:

> Sure, one can do nasty async design in schematics, or in VHDL for that
> matter. But S/360 and Cray and the HP35 and moon rockets were designed
> before HDLs, and they worked fine. Some people were good at logic
> design a long time before FPGAs were invented.
> 
And some people are still quite lousy with logic design despite having 
FPGAs and the best HDLs.  HDLs do not make a good logic designer, they 
are simply a tool.

On Fri, 6 Jan 2006 08:52:13 +0000 (UTC), Uwe Bonnes
<bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

>John  Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote:
>> On Wed, 4 Jan 2006 22:08:26 +0000 (UTC), Uwe Bonnes
>> <bon@hertz.ikp.physik.tu-darmstadt.de> wrote:
>
>> >Mike Treseler <mike_treseler@comcast.net> wrote:
>> >> Austin Lesea wrote:
>> >
>> >> > I would invest my time in learning a HDL:  VHDL or Verilog.
>> >
>> >> Good advice, but allow several months.
>> >
>> >But schematic entry oftem leads to non-registered designs, where you should
>> >allow several month of debugging too... 
>
>> Why? Logic is logic. We do lots of complex designs, state machines and
>> all, in schematic form, and they come up in days or hours.
>
>If you do registered designs and don't relay on some function having some
>definite delay, things will be fine. However many TTL designs are created
>different...

Sure, one can do nasty async design in schematics, or in VHDL for that
matter. But S/360 and Cray and the HP35 and moon rockets were designed
before HDLs, and they worked fine. Some people were good at logic
design a long time before FPGAs were invented.

I don't have time to learn an HDL. I read the Xilinx book, draw
schematics (on paper!), and hand them to a minion to enter and
compile. Works great.

John

Concur, definitely Altera. Xilinx schematic entry and conversion to HDL
is full of bugs.

Rob wrote:
> Definitely Altera.
>
> "Thomas Entner" <aon.912710880@aon.at> wrote in message
> news:43bc292b$0$16891$91cee783@newsreader01.highway.telekom.at...
> >> I'm looking at doing some basic CPLD designs via Schematic Entry.  Who
> >> has easier to learn/use schematic entry software, Xilinx or Altera?
> >
> > Altera
> >
> > Regards,
> >
> > Thomas
> >

John  Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote:
> On Wed, 4 Jan 2006 22:08:26 +0000 (UTC), Uwe Bonnes
> <bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

> >Mike Treseler <mike_treseler@comcast.net> wrote:
> >> Austin Lesea wrote:
> >
> >> > I would invest my time in learning a HDL:  VHDL or Verilog.
> >
> >> Good advice, but allow several months.
> >
> >But schematic entry oftem leads to non-registered designs, where you should
> >allow several month of debugging too... 

> Why? Logic is logic. We do lots of complex designs, state machines and
> all, in schematic form, and they come up in days or hours.

If you do registered designs and don't relay on some function having some
definite delay, things will be fine. However many TTL designs are created
different...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On Wed, 4 Jan 2006 22:08:26 +0000 (UTC), Uwe Bonnes
<bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

>Mike Treseler <mike_treseler@comcast.net> wrote:
>> Austin Lesea wrote:
>
>> > I would invest my time in learning a HDL:  VHDL or Verilog.
>
>> Good advice, but allow several months.
>
>But schematic entry oftem leads to non-registered designs, where you should
>allow several month of debugging too... 

Why? Logic is logic. We do lots of complex designs, state machines and
all, in schematic form, and they come up in days or hours.

John