Hi - 

If the system you're designing is a one-off, there's no harm in trying
various things to see what works.  But if you plan to make multiple
copies of this design, there's no substitute for timing analysis.  And
you don't need fancy tools: use Excel if you have it, paper and pencil
if you don't.

Without the timing analysis, it's just guessing.

Bob Perlman
Cambrian Design Works  

On Wed, 11 Jan 2006 07:42:47 -0600, "Pouria" <pouria@hotmail.com>
wrote:

>HI Everybody!
>
>I'm having a timing problem interfacing with my SDRAM bank. I'm using
>256Mb MT48LC16M16 SDRAM from Micron, and want to operate them  at 100 Mhz.
>So far I have only been working at 40 Mhz.
>
>I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
>for clocking the SDRAM. The design works if I DON'T use the external
>feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
>the feedback (Which according to Xilinx should be the correct way to
>terminate clock Skew). 
>
>The feedback to the other DLL is taken from clock output of it self, and I
>have used IBUG/OBUF/BUFG so that is not the problem.
>
>Hope some one can help me .
>Best regards,
>/P
>
> 
>
>

Joseph Samson wrote:
> > Pouria wrote:
> >
> >>HI Everybody!
> >>
> >>I'm having a timing problem interfacing with my SDRAM bank. I'm using
> >>256Mb MT48LC16M16 SDRAM from Micron, and want to operate them  at 100 Mhz.
> >>So far I have only been working at 40 Mhz.
> >>
> >>I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
> >>for clocking the SDRAM. The design works if I DON'T use the external
> >>feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
> >>the feedback (Which according to Xilinx should be the correct way to
> >>terminate clock Skew).
> >>
> >>The feedback to the other DLL is taken from clock output of it self, and I
> >>have used IBUG/OBUF/BUFG so that is not the problem.
>
> As Gabor pointed out, register all signals in the IOBs and use fast slew
> rate drivers. I highly recommend using the DDR IOB flipflop to generate
> the SDRAM clock. That dramatically improved my SDRAM design, and now I
> generate all external clocks that way. You might have good luck sending
> an inverted clock to the SDRAMs. I don't use the clock feedback.
>
> Once you get the design running, experiment with lowering the output
> drive. The default is 12mA, but my layout allows me to go as low as 4mA.
>
> ---
> Joe Samson
> Pixel Velocity

That's a good point about using the IOB flip-flop.  In Virtex II you
can use the
DDR flip-flop to output a clock at the same frequency that clocks the
flip-flop.
The timing will match clock-to-out on other IOB flip-flops that use the
single
output flip-flop (it's really the same hardware).  If you use a single
clock in the
design you'll have hold-time issues at the SDRAM because your data,
address,
and control signals will coincide with the rising clock edge (0 hold
time).  Use
a DCM to generate a delayed clock for everything other than the SDRAM
clock outputs.  If the delay between clocks is small, just enough to
meet
SDRAM hold time requirements, you shouldn't have hold time issues on
your
input registers (but don't assign NODELAY to the input nets).

Also note that lowering the output drive increases the output clock to
Q time.
You can use this selectively to intentionally add skew between signals
if
necessary (but not a lot).  I often drive clock outputs with higher
current to
slightly advance the timing with respect to other signals.

Good Luck,
Gabor

> Pouria wrote:
> 
>>HI Everybody!
>>
>>I'm having a timing problem interfacing with my SDRAM bank. I'm using
>>256Mb MT48LC16M16 SDRAM from Micron, and want to operate them  at 100 Mhz.
>>So far I have only been working at 40 Mhz.
>>
>>I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
>>for clocking the SDRAM. The design works if I DON'T use the external
>>feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
>>the feedback (Which according to Xilinx should be the correct way to
>>terminate clock Skew).
>>
>>The feedback to the other DLL is taken from clock output of it self, and I
>>have used IBUG/OBUF/BUFG so that is not the problem.

As Gabor pointed out, register all signals in the IOBs and use fast slew 
rate drivers. I highly recommend using the DDR IOB flipflop to generate 
the SDRAM clock. That dramatically improved my SDRAM design, and now I 
generate all external clocks that way. You might have good luck sending 
an inverted clock to the SDRAMs. I don't use the clock feedback.

Once you get the design running, experiment with lowering the output 
drive. The default is 12mA, but my layout allows me to go as low as 4mA.

---
Joe Samson
Pixel Velocity

Pouria wrote:
> HI Everybody!
>
> I'm having a timing problem interfacing with my SDRAM bank. I'm using
> 256Mb MT48LC16M16 SDRAM from Micron, and want to operate them  at 100 Mhz.
> So far I have only been working at 40 Mhz.
>
> I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
> for clocking the SDRAM. The design works if I DON'T use the external
> feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
> the feedback (Which according to Xilinx should be the correct way to
> terminate clock Skew).
>
> The feedback to the other DLL is taken from clock output of it self, and I
> have used IBUG/OBUF/BUFG so that is not the problem.
>
> Hope some one can help me .
> Best regards,
> /P

This really sounds like you are getting hold time violations.  I think
for standard
single-data-rate SDRAM 100 MHz should be very easy to attain if you
register
everything in the IOB's, and your clocks at the SDRAM and Virtex are in
phase.
In my past designs with these parts I distributed the 100 MHz from a
central
clock resource to the SDRAM chips and the FPGA.  I was able to run
without
using DLL or DCM at 100 MHz, just using the clock from a global input
pin
through the associated BUFG.  Thus my internal clock was somewhat
delayed
from the SDRAM clock, but using the standard IOB input timing there
should
be no hold time violation.  It is important to use fast slew rate on
the output
buffers or you will definitely get setup time violations at the SDRAM.

HI Everybody!

I'm having a timing problem interfacing with my SDRAM bank. I'm using
256Mb MT48LC16M16 SDRAM from Micron, and want to operate them  at 100 Mhz.
So far I have only been working at 40 Mhz.

I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one
for clocking the SDRAM. The design works if I DON'T use the external
feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use
the feedback (Which according to Xilinx should be the correct way to
terminate clock Skew). 

The feedback to the other DLL is taken from clock output of it self, and I
have used IBUG/OBUF/BUFG so that is not the problem.

Hope some one can help me .
Best regards,
/P