Hi Alessandro,

There are a few options...

use Speedgrade 6,
use the Pineline option in the SOPC Builder clock setup,
split your design in a 100MHz, and lower speedpart.... (which will
introduce big latencies when crossing the clock domains, but enables
the 100 MHz logic to be small and therefore fast)

Maybe you can be happy with the standard or economy core. They might
have a higher fmax, to match your speed, but give lower MIPS.

Have fun !

Dear everybody,

I have developed a NIOS II based project which must run on a Cyclone
with speed grade 7.
The project contains only a NIOS II/f configuration which includes the
following pheriperals:
   - SRAM interface designed with user custom logic
   - common flash interface
   - one interval timer
   - three uarts
   - two tightly coupled on-chip memory blocks
   - one on-chip memory block used as boot ROM

The input clock is 100 Mhz (derived by 25 MHz FPGA input clock
multiplied by PLL).

The compilation flow runs successfully except for the timing analyzer
which issues a
critical warning says the timing requirements are not met. Taking a
look at the timing
analyzer summary report I see that the fmax of the project is 74.56 MHz
(against my
desidered fmax of 100 MHz). I have tried to get timing analyzer run
successfully by
changing some fitter options but the results are the same. At the end
of the compilation
flow the summary reports that the resources needed by the project are
32 % of the
device.

First question: is 74.56 MHz a fmax limit of NIOS II/f integrated on a
Cyclone device ?
Second question: is there a way to improve the fmax in order to match
my desidered
frequency ?

Best Regards

/Alessandro Strazzero