Marco wrote:
> Leon, sorry, could you explain me more in detail what you've done?
> Thanks

'Bit-banging' is slang for clocking out the data by manipulating pins
with software, instead of using hardware, which is how it is done in
the SPORTs. It's often used for asynchronous comms (a software UART),
and for synchronous protocols like SPI, and FPGA configuration.

It was a long time ago, and t've got the software somewhere. It was
quite straightforward, using the Altera documentation.

Leon

Leon, sorry, could you explain me more in detail what you've done?
Thanks

When I had to interface an Altera device to an ADSP-2187, I simply
bit-banged the configuration into the FPGA., rather than use the SPORT.
The latter was also needed for data transfer, and it seemed easier to
do it that way.

Leon

The CCLK pin goes High-Z after configuration and this lets me use the
signal put in parallel to work with the same DSP input, what about the
DONE pin? It seems I can't I convert it to High-Z too, right?
Thanks

Thanks Antti, I'll go with option 2 as long as I have to use Spartan3,
do you think there's something I should take particular care about
working this way? I'll need to do the same for the DONE signal, in
order not to waste the DSP input.
Thanks, Marco

"Marco" <marco@marylon.com> schrieb im Newsbeitrag 
news:1137516377.278102.203140@z14g2000cwz.googlegroups.com...
> Hi, I have to initialize a Spartan3 with a Blackfin DSP. I was thinking
> to connect the CCLK and DIN pins to the serial port of the DSP (SPORT),
> but while the DIN is dual-purpose, the CCLK is dedicated. I'll then
> need, when all properly configured, FPGA and DSP to communicate with
> the SPORT once again for the normal work of the board.
> Here comes the issue because the CCLK used for the initialization has
> to be substituted with the serial protocol clock (as long as the former
> is a dedicated one and no more available after start-up).
> What do you suggest me to do? To put the 2 clock of the Spartan3 on the
> same path to the input pin of the SPORT clock on the DSP side, keeping
> the normal clock on high impedance during the configuration, ie when
> the initialization clock works, and the opposite after the setup
> process?
> Anyone had to solve similar issues?
> Thanks in advance,
> Marco
>
2 options

1) use Spartan3e there CCLK is dual purpose
2) add user IO in parallel to CCLK to be able to use it after configuration, 
the 'normal' clock is automatically tri stated when FPGA is not configured 
so it want matter, as long as the DSP can pull prog_b to force 
(re)configuration

-- 
Antti Lukats
http://www.xilant.com 

Hi, I have to initialize a Spartan3 with a Blackfin DSP. I was thinking
to connect the CCLK and DIN pins to the serial port of the DSP (SPORT),
but while the DIN is dual-purpose, the CCLK is dedicated. I'll then
need, when all properly configured, FPGA and DSP to communicate with
the SPORT once again for the normal work of the board.
Here comes the issue because the CCLK used for the initialization has
to be substituted with the serial protocol clock (as long as the former
is a dedicated one and no more available after start-up).
What do you suggest me to do? To put the 2 clock of the Spartan3 on the
same path to the input pin of the SPORT clock on the DSP side, keeping
the normal clock on high impedance during the configuration, ie when
the initialization clock works, and the opposite after the setup
process?
Anyone had to solve similar issues?
Thanks in advance,
Marco