On Mon, 23 Jan 2006 09:43:02 +0100, "Frank Schreiber" <frankschr@googlemail.com> wrote:
>Dear all,
>I am using Virtex 4 from Xillinx, and I really missed the clock for LVDS.
>So, should I transfer data to LVDS each time posedge of the clock.
>The clock should be LVDS clock, LTTL clock or any clock is possible.
>Many thanks
>Frank

I don't understand you Frank! Multiple times others have
explained to you that if you don't give sufficient information,
it is IMPOSSIBLE to answer your questions.

Give the following information, and maybe you can be helped:

1) Which exact Xilinx part number are you using.

2) What EXACT device (part number) are you connecting it to

3) How many wires total have you connected between these chips,
   (LVDS should be 2 wires per signal, 8 data + clock would total
    to 18 wires)

4) Bonus info would be the manufacturer of the board (or if it
   is your own design, some more details of the design and the
   purpose), the clock rate you are trying to use, whether the
   data is single or double data rate.



Philip Freidin
Fliptronics

Are you trying to implement the transmitter within the FPGA?

"Frank Schreiber" <frankschr@googlemail.com> wrote in message 
news:dr0fec$kvu$1@anderson.hrz.tu-chemnitz.de...
> Dear all
> I'm starting with LVDS.
> My task is sending 8-bits signal to LVDS Transmitter port on my board.
> I declared a 8 bits vector, assigned pins, and changed values in 8-bits
> signal, but nothing happended in my oscilloscope. Assume that pins-out are
> right assigned, all wires and DAC are working perfectly.
> Can anyone advise me, how to make it works.
> Many thanks
> Frank
>
> 

Frank,
From your IP address I guess you're a Physics student at university. I'd 
suggest you go down the corridor to the EE department and ask someone there 
who will be able to help you face to face. Even if they can't answer your 
question, they could probably tell you what to post here to get an answer.
HTH and good luck, Syms.
"Frank Schreiber" <frankschr@googlemail.com> wrote in message 
news:dr0fec$kvu$1@anderson.hrz.tu-chemnitz.de...
> Dear all
> I'm starting with LVDS.
> My task is sending 8-bits signal to LVDS Transmitter port on my board.
> I declared a 8 bits vector, assigned pins, and changed values in 8-bits
> signal, but nothing happended in my oscilloscope. Assume that pins-out are
> right assigned, all wires and DAC are working perfectly.
> Can anyone advise me, how to make it works.
> Many thanks
> Frank
>
> 

"Frank Schreiber" <frankschr@googlemail.com> schrieb im Newsbeitrag 
news:dr26uq$n0i$1@anderson.hrz.tu-chemnitz.de...
> So,
> in this case should I provide 8 bits for data, and 1 bits for clock ?
> Any clock else ?
> Frank
>>

if you have a DAC chip with 8 bit DDR LVDS then you have 8 bit data in FPGA 
and 1 bit clock, and there will be 16 actual data wires(8 +- pairs)) from 
FPGA and 2 clock lines (1 +- pair)

but you can not expect to get help if you dont say what is the thing that is 
connnected to FPGA, I assume its an high speed digital analog converter, but 
only you know it for sure, others can only guess

-- 
Antti Lukats
http://www.xilant.com 

So,
in this case should I provide 8 bits for data, and 1 bits for clock ?
Any clock else ?
Frank
>
>
> think of LVDS that you use 2 wires an not 1 for 1 signal
>
> for LVDS its irrelevant if the signal is clock or data or whatever
>
> what I said is that if you have DAC chip that uses LVDS standard then this
> DAC chip does need a LVDS clock to latch the data, but its only my guess,
> you really did not provide enough info.
>
>
> --
> Antti Lukats
> http://www.xilant.com
>
>

"Frank Schreiber" <frankschr@googlemail.com> schrieb im Newsbeitrag 
news:dr25fb$ii6$1@anderson.hrz.tu-chemnitz.de...
> Hi Peter
> It's nice that you mentioned. But truely that I don't know much, so I
> provided a little bit informations.
> But I think other informations are not so important: LVDS are standard, 
> and
> it does the same way in different boards. The most important thing that I
> don't know is how it works. Antti said that it needs a clock....
> Many thanks


think of LVDS that you use 2 wires an not 1 for 1 signal

for LVDS its irrelevant if the signal is clock or data or whatever

what I said is that if you have DAC chip that uses LVDS standard then this 
DAC chip does need a LVDS clock to latch the data, but its only my guess, 
you really did not provide enough info.


-- 
Antti Lukats
http://www.xilant.com

Hi Peter
It's nice that you mentioned. But truely that I don't know much, so I
provided a little bit informations.
But I think other informations are not so important: LVDS are standard, and
it does the same way in different boards. The most important thing that I
don't know is how it works. Antti said that it needs a clock....
Many thanks
Frank.
"Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:1137958167.597749.115710@g49g2000cwa.googlegroups.com...
> Frank, be serious:
> You do not tell us which FPGA family and which board. You don't report
> that you have tried a different output standard. You mention little
> about your design and environment.
> How can you possibly expect any meaningful help?
> It's like calling a doctor: "What should I do, it hurts!"
> Peter Alfke
>

Dear all,
I am using Virtex 4 from Xillinx, and I really missed the clock for LVDS.
So, should I transfer data to LVDS each time posedge of the clock.
The clock should be LVDS clock, LTTL clock or any clock is possible.
Many thanks
Frank

"Antti Lukats" <antti@openchip.org> wrote in message
news:dr0n2t$7i5$1@online.de...
> Maxim, ADI and TI LVDS DACs all require LVDS clock to latch the data,
unless
> you provide some meaningful data on the output and suitable clock do not
> expect anything.
>
> you said "assume" all wires and DAC are working,  well assuming that all
> should work as long as you made some meaningful (as per DAC datasheet
spec)
> singals on the LVDS data and clock outputs.
>
> Antti
>
>

Not entirely clear to me that he is looking at the DAC output from those 
words. Didn't even say that the oscilloscpe was actually connected never 
mind what to.

Frank give us all a bit more info. We might be assuming something or nothing 
correctly. The old swing on the tree graphic is coming to mind.

John Adair
Enterpoint Ltd. - We're at DATE2006. Come and say hello.
http://www.enterpoint.co.uk


"Antti Lukats" <antti@openchip.org> wrote in message 
news:dr0p4c$bs9$1@online.de...
> Hi John,
>
> he is looking at DAC output not at LVDS signals. he said assume the wires 
> __and__ DAC are working properly, so hes oscilloscope is on the output of 
> an LVDS DAC
>
> Antti
>
> "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> schrieb 
> im Newsbeitrag news:dr0oor$gck$1@newsg2.svr.pol.co.uk...
>> Frank
>>
>> Remember to check the scale on your oscilloscpe. The LVDS signal is very 
>> small and easy to miss if setup for something like TTL levels. I've done 
>> that before myself. If you are using Xilinx you can check if LVDS is 
>> implemented from the pin file I think or do it my favorite way in by 
>> looking at the design in FPGA editor.
>>
>> John Adair
>> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
>> Board.
>> http://www.enterpoint.co.uk
>>
>> "Frank Schreiber" <frankschr@googlemail.com> wrote in message 
>> news:dr0fec$kvu$1@anderson.hrz.tu-chemnitz.de...
>>> Dear all
>>> I'm starting with LVDS.
>>> My task is sending 8-bits signal to LVDS Transmitter port on my board.
>>> I declared a 8 bits vector, assigned pins, and changed values in 8-bits
>>> signal, but nothing happended in my oscilloscope. Assume that pins-out 
>>> are
>>> right assigned, all wires and DAC are working perfectly.
>>> Can anyone advise me, how to make it works.
>>> Many thanks
>>> Frank
>>>
>>>
>>
>>
>
> 

Hi John,

he is looking at DAC output not at LVDS signals. he said assume the wires 
__and__ DAC are working properly, so hes oscilloscope is on the output of an 
LVDS DAC

Antti

"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> schrieb 
im Newsbeitrag news:dr0oor$gck$1@newsg2.svr.pol.co.uk...
> Frank
>
> Remember to check the scale on your oscilloscpe. The LVDS signal is very 
> small and easy to miss if setup for something like TTL levels. I've done 
> that before myself. If you are using Xilinx you can check if LVDS is 
> implemented from the pin file I think or do it my favorite way in by 
> looking at the design in FPGA editor.
>
> John Adair
> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
> Board.
> http://www.enterpoint.co.uk
>
> "Frank Schreiber" <frankschr@googlemail.com> wrote in message 
> news:dr0fec$kvu$1@anderson.hrz.tu-chemnitz.de...
>> Dear all
>> I'm starting with LVDS.
>> My task is sending 8-bits signal to LVDS Transmitter port on my board.
>> I declared a 8 bits vector, assigned pins, and changed values in 8-bits
>> signal, but nothing happended in my oscilloscope. Assume that pins-out 
>> are
>> right assigned, all wires and DAC are working perfectly.
>> Can anyone advise me, how to make it works.
>> Many thanks
>> Frank
>>
>>
>
>