Reply by Antonio Roldao Lopes●February 8, 20062006-02-08
This issue seems to be fixed with the newer ISE version ( 8.1i ).
Thank-you Aurelian Lazarut, for you support.
Roldao
Antonio Roldao Lopes wrote:
> Greetings FPGA Group,
>
> I'm attempting to input an LVDS clock signal into a SoC design. This
> development is based on a NuHorizons SP3 board with a Spartan-3
> (xc3s1500-fg676-4). Although it supports primitives for input
> differential clock signals through the usage of, for example, the
> IBUFGDS_LVDS_25 component, when I do instantiate such blocks, Bitgen
> reports a couple of non-informative warnings and finally generates the
> stream. However the result corrupts all the internal signals of the
> SoC...
>
> The warnings only show up with the Spartan-3 family. All works fine,
> and no warnings are displayed if using a Virtex family device. These
> warnings as following pop-up during the bit-generation (using ISE
> 7.1i):
>
> WARNING:Bitgen:74 - Unknown primitive "DRIVE_0MA" for site "IOB4".
> WARNING:Bitgen:74 - Unknown primitive "DRIVE_0MA" for site "IOB5".
>
> Any help, hint, or even pointers to successful implementations of LVDS
> clocks inputs on a Spartan 3, will be mostly appreciated.
>
> Thanks in Advance,
> Antonio Roldao Lopes
>
> I've isolated the code that generates such warnings and produced a
> simple test-bench, here it goes...
>
> -- LVDS BLACK BOX
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> library UNISIM;
> use UNISIM.VComponents.all;
>
> entity LVDS_BOX is
> port(nRESET : in std_logic;
> CLK_T : in std_logic;
> CLK_I : in std_logic;
> CLK_O : out std_logic);
> end LVDS_BOX;
>
> architecture Behavioral of LVDS_BOX is
>
> signal CLK : std_logic;
> signal s : std_logic;
>
> begin
>
> U0: IBUFGDS_LVDS_25 port map (I=>CLK_T,IB=>CLK_I,O=>CLK);
>
> process(nRESET, CLK)
> begin
> if nRESET = '0' then
> s <= '0';
> elsif rising_edge(CLK) then
> s <= not s;
> end if;
> end process;
>
> CLK_O <= s;
>
> end Behavioral;
>
>
>
> -- TEST BENCH LVDS BLACK BOX
>
> LIBRARY ieee;
> USE ieee.std_logic_1164.ALL;
> USE ieee.std_logic_unsigned.all;
> USE ieee.numeric_std.ALL;
>
> ENTITY Tb_LVDS_BOX IS
> END Tb_LVDS_BOX;
>
> ARCHITECTURE behavior OF Tb_LVDS_BOX IS
>
> COMPONENT LVDS_BOX
> PORT(
> nRESET : IN std_logic;
> CLK_T : IN std_logic;
> CLK_I : IN std_logic;
> CLK_O : OUT std_logic
> );
> END COMPONENT;
>
> --Inputs
> SIGNAL nRESET : std_logic := '0';
> SIGNAL CLK_T : std_logic := '0';
> SIGNAL CLK_I : std_logic := '1';
>
> --Outputs
> SIGNAL CLK_O : std_logic;
>
> BEGIN
>
> -- Instantiate the Unit Under Test (UUT)
> uut: LVDS_BOX PORT MAP(nRESET,CLK_T,CLK_I,CLK_O);
>
> -- Generate Differential Clock Signal
> CLK_T <= not CLK_T after 100 ns;
> CLK_I <= not CLK_I after 100 ns;
>
> tb : PROCESS
> BEGIN
> -- Reset System
> nRESET <= '0';
> wait for 400 ns;
> nRESET <= '1';
>
> -- Stop Simlation, the ugly way!
> wait for 1 us;
> report "Done" severity Failure;
> END PROCESS;
>
> END;
Reply by Antonio Roldao Lopes●February 7, 20062006-02-07
Greetings FPGA Group,
I'm attempting to input an LVDS clock signal into a SoC design. This
development is based on a NuHorizons SP3 board with a Spartan-3
(xc3s1500-fg676-4). Although it supports primitives for input
differential clock signals through the usage of, for example, the
IBUFGDS_LVDS_25 component, when I do instantiate such blocks, Bitgen
reports a couple of non-informative warnings and finally generates the
stream. However the result corrupts all the internal signals of the
SoC...
The warnings only show up with the Spartan-3 family. All works fine,
and no warnings are displayed if using a Virtex family device. These
warnings as following pop-up during the bit-generation (using ISE
7.1i):
WARNING:Bitgen:74 - Unknown primitive "DRIVE_0MA" for site "IOB4".
WARNING:Bitgen:74 - Unknown primitive "DRIVE_0MA" for site "IOB5".
Any help, hint, or even pointers to successful implementations of LVDS
clocks inputs on a Spartan 3, will be mostly appreciated.
Thanks in Advance,
Antonio Roldao Lopes
I've isolated the code that generates such warnings and produced a
simple test-bench, here it goes...
-- LVDS BLACK BOX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity LVDS_BOX is
port(nRESET : in std_logic;
CLK_T : in std_logic;
CLK_I : in std_logic;
CLK_O : out std_logic);
end LVDS_BOX;
architecture Behavioral of LVDS_BOX is
signal CLK : std_logic;
signal s : std_logic;
begin
U0: IBUFGDS_LVDS_25 port map (I=>CLK_T,IB=>CLK_I,O=>CLK);
process(nRESET, CLK)
begin
if nRESET = '0' then
s <= '0';
elsif rising_edge(CLK) then
s <= not s;
end if;
end process;
CLK_O <= s;
end Behavioral;
-- TEST BENCH LVDS BLACK BOX
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY Tb_LVDS_BOX IS
END Tb_LVDS_BOX;
ARCHITECTURE behavior OF Tb_LVDS_BOX IS
COMPONENT LVDS_BOX
PORT(
nRESET : IN std_logic;
CLK_T : IN std_logic;
CLK_I : IN std_logic;
CLK_O : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL nRESET : std_logic := '0';
SIGNAL CLK_T : std_logic := '0';
SIGNAL CLK_I : std_logic := '1';
--Outputs
SIGNAL CLK_O : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LVDS_BOX PORT MAP(nRESET,CLK_T,CLK_I,CLK_O);
-- Generate Differential Clock Signal
CLK_T <= not CLK_T after 100 ns;
CLK_I <= not CLK_I after 100 ns;
tb : PROCESS
BEGIN
-- Reset System
nRESET <= '0';
wait for 400 ns;
nRESET <= '1';
-- Stop Simlation, the ugly way!
wait for 1 us;
report "Done" severity Failure;
END PROCESS;
END;