> I am routing a pcb with a fpga and adc which has LVDS outputs. I am trying
> to match the length of the signals. Will I be ok to match them to within
> 1mm. The max length of any signal will be 33mm and the adc is clocked at
> 250MHz.
Yes, the apr. 6 pS skew because of the 1mm should
be negligible. In fact, I would say you'd still be safe with
10 times as much skew (10 mm length matching).
Dimiter
------------------------------------------------------
Dimiter Popoff Transgalactic Instruments
http://www.tgi-sci.com
------------------------------------------------------
Reply by Allan Herriman●February 11, 20062006-02-11
On Sat, 11 Feb 2006 07:10:21 -0600, "maxascent"
<maxascent@yahoo.co.uk> wrote:
>I am routing a pcb with a fpga and adc which has LVDS outputs. I am trying
>to match the length of the signals. Will I be ok to match them to within
>1mm. The max length of any signal will be 33mm and the adc is clocked at
>250MHz.
Short answer: yes.
Long answer:
I'm not quite clear about whether you mean length matching between the
various bits coming out of the ADC, or length matching between the P
and N signals in an LVDS pair of a single bit.
1. Assume that you are referring to the length match between the bits
within the bus.
Divide 1mm by the speed of light in epoxy to get the skew between the
signals. My mental ALU says this works out to be about 5ps. Note
that this is *skew*. You still have to ensure adequate timing margin
for each signal in the bus. In this sense, the skew reduces your
timing margin, however, if you have to worry about 5ps when your clock
has a 4ns period, you have much bigger problems on your hands.
2. Assume you are referring to the length match between the P and N
signals in an LVDS pair of an individual bit.
Normally for data signals this would be treated as in case 1, however
an ADC is sensitive to noise, and a length mismatch may result in a
small amount of differential mode to common mode conversion. You
might want to do some spice modelling here, however I don't expect
you'll have a problem.
Also bear in mind that 1mm is probably better than the length match
inside the BGA package. (I'm referring to the tracks between the
solder balls and the die pads.) If you get really keen, you can
determine these lengths, and adjust the the lengths of the traces on
your pcb to compensate.
I did this once for a couple of 16 bit 622MHz buses. It was a PITA to
do, and probably didn't make much real difference (it might have
changed the eye width from 73 to 74% or something like that). The PCB
guy decided to change to software programming after that project.
Since then, we've changed to Expedition PCB from Mentor, and the (new)
PCB guy here says length matching including offsets is really easy to
do.
Another caveat: the velocity factor of a trace differs depending on
the layer inside the PCB. Outer layers propagate signals faster due
to the lower effective permittivity! This can cause problems with
length matching if you are not careful. A good PCB tool will allow
you to specify the velocity factor independently for each layer.
Regards,
Allan
Reply by maxascent●February 11, 20062006-02-11
I am routing a pcb with a fpga and adc which has LVDS outputs. I am trying
to match the length of the signals. Will I be ok to match them to within
1mm. The max length of any signal will be 33mm and the adc is clocked at
250MHz.
Thanks
Jon