When I saw the little "updated" icon next to the link on Xilinx site, I
thought you might have read an older version ;)

This particular info has been added in the 1.4 revision from the 24th
January 2006. (Check the revision history at the beginning of the
document for more details on the changes)

Actually I just checked my printed version of the UG701, and on the
version 1.2 (August 8, 2005) it is not present.

Bad luck I suppose, since I printed this version only 2 weeks ago (but
I don't remember if I took the version on my computer or the version
published on xilinx.com by this time).

Morality is: I should always check for updated version.

Damn! You're totally right. That's incredible I just couldn't see it!

Thanks a lot, I should read more carefully.

Bertrand

What about Table 7-5 of ug071.pdf (page 91) ?

http://direct.xilinx.com/bvdocs/userguides/ug071.pdf

Hi,

Actually my work is not about bitstream generation, but bitstream
manipulation. I'd like to be able to do some readback operation on my
design and replace some parts with another design (partial
reconfiguration). Bitstreams  will still be generated by xilinx tools
and stored in memory, so I'm not generating bitstreams.

But I need to be able to address frames in the device in order to make
my design possible. Frame addressing for virtex-4 is - as far as I know
- undocumented (altough frame addressing for V-II devices is quite well
documented), that's why I was wondering if anyone had a clue about this
subject.

But thanks for the discussion, I did not see it on the list, it is sure
a good read to have.

Hi Bertrand,

did you have a look at the discussion "Xilinx legal" posted here by 
Austin Leslea on 30.01.2006 ?
You won't be allowed to perform bitstream creation...

Stephane


Bertrand Rousseau wrote:
> Hi everyone,
> 
> I'm trying to understand how the frame addresses have to be decoded for
> a Virtex-4 FPGA from Xilinx. So far I could find documentation about
> the configuration for VI and VII FPGAs, but there seem to be small
> modifications between these models frame addresses and the new
> Virtex-4.
> 
> Has anyone already tried to understand frame addresses in Virtex-4?
> 
> Thanks
> 
> Bertrand
> 

Hi everyone,

I'm trying to understand how the frame addresses have to be decoded for
a Virtex-4 FPGA from Xilinx. So far I could find documentation about
the configuration for VI and VII FPGAs, but there seem to be small
modifications between these models frame addresses and the new
Virtex-4.

Has anyone already tried to understand frame addresses in Virtex-4?

Thanks

Bertrand