But I have attached my IP and the BRAM on the PLB why the connection
between OPB and PLB

Mich

you need to read the IPIF documentation, this is an middle IP layer
that is used to connect things to OPB and PLB

antti

Hi

tanks for the help

I have looked up the appnote for using BRAM and the PLB-bus.
They speak of "IP2IP_Addr but what those that means?
I think I don't have addresses in my IP or do I have them and I don't
know about it.
How can you have addresses in your IP?

Can anyone tell me more about this?

Greets
Mich

Mich wrote:
> Hi all,
> 
> I'm designing a IP core for a Virtex 2 pro board. This IP need to store
> data in BRAM. I have been searching how I can adress the BRAM with my
> IP but I haven't found it.
> Can anyone tell me how you can do this?
> 
> Thanks
> Mich
> 

Short coding example (from the real life):

--snip
type memory_type is array (natural range <>) of std_logic_vector(0 to 31);
signal memory : memory_type(511 downto 0);
--snap
--snip
bram_inst : process(clk) is
begin
   if rising_edge(clk) then
     if rst = '1' then
       data_out <= (others => '0');
     else
       if fifo_write = '1' then
         memory(to_integer(write_addr)) <= data_in;
       else
         data_out <= memory(to_integer(read_addr));
       end if;
     end if;
   end if;
end process;
--snap

This process infers a BRAM (at least if synthesized by ISE). data_out 
and data_in are obviously global ports. write_addr is a counter keeping 
track of where to write (this BRAM was used in a FIFO) and read_addr is 
equally a counter keeping track of where to read. to_integer() is a 
function converting a std_logic_vector to an integer.

Apart from this you may implement logic for full- and empty flags etc.

-- 
-----------------------------------------------
Johan Bernsp&#4294967295;ng, xjohbex@xfoix.se
Research engineer

Swedish Defense Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

It is simple and straightforward, but remember that reading (as well as
writing) requires a clock.
And you must provide stable addresses a set-up time before the active
clock edge, not only for writing, but also for reading.
Peter Alfke, Xilinx, from home.

Mich wrote:
> Hi all,
>
> I'm designing a IP core for a Virtex 2 pro board. This IP need to store
> data in BRAM. I have been searching how I can adress the BRAM with my
> IP but I haven't found it.
> Can anyone tell me how you can do this?
>
> Thanks
> Mich

Look at Xilinx's website for an appnote. It is not difficult to
interface with BRAM's.

Hi all,

I'm designing a IP core for a Virtex 2 pro board. This IP need to store
data in BRAM. I have been searching how I can adress the BRAM with my
IP but I haven't found it.
Can anyone tell me how you can do this?

Thanks
Mich