On 01 Mar 2006 15:37:30 -0800, Eric Smith <eric@brouhaha.com> wrote:

>+<"nezhate" <mazouz.nezhate@gmail.com> writes:
>+<> Hi all, I want to use a small cricuit (written in verilog and was
>+<> designed using ISE 3) in an other project using ISE 8.1. the problem is
>+<> that under ISE 3 the circuit worked perfectly, and under ISE 8.1 the is
>+<> an error. why this occur ?
>+<
>+<Probably because you're not rubbing together a regurgitative purwell and
>+<a supramitive wennelsprock.
>+<
>+<You might get better results after reading:
>+<
>+<    http://www.catb.org/~esr/faqs/smart-questions.html
*****

Oh no the net police!!!

james

Can you post the error, so we can take a look ?

Aurash

nezhate wrote:
> Hi all, I want to use a small cricuit (written in verilog and was
> designed using ISE 3) in an other project using ISE 8.1. the problem is
> that under ISE 3 the circuit worked perfectly, and under ISE 8.1 the is
> an error. why this occur ?
> 

"nezhate" <mazouz.nezhate@gmail.com> writes:
> Hi all, I want to use a small cricuit (written in verilog and was
> designed using ISE 3) in an other project using ISE 8.1. the problem is
> that under ISE 3 the circuit worked perfectly, and under ISE 8.1 the is
> an error. why this occur ?

Probably because you're not rubbing together a regurgitative purwell and
a supramitive wennelsprock.

You might get better results after reading:

    http://www.catb.org/~esr/faqs/smart-questions.html

Gabor wrote:
> nezhate wrote:
> 
>>Hi all, I want to use a small cricuit (written in verilog and was
>>designed using ISE 3) in an other project using ISE 8.1. the problem is
>>that under ISE 3 the circuit worked perfectly, and under ISE 8.1 the is
>>an error. why this occur ?
> 
> 
> Was the error in the operation of the circuit or in synthesizing the
> circuit.
> 
> I've noticed that in 8.1i leaving output ports undriven results in an
> error
> when you get to BitGen, while in 6.1i and earlier these nets were just
> ripped out of the design in mapping.

  Have you mentioned that to Xilinx ? - just in case their
"extensive regression testing" missed this.
  Sounds like yet another oops, that needs fixing...

-jg

nezhate wrote:
> Hi all, I want to use a small cricuit (written in verilog and was
> designed using ISE 3) in an other project using ISE 8.1. the problem is
> that under ISE 3 the circuit worked perfectly, and under ISE 8.1 the is
> an error. why this occur ?

Was the error in the operation of the circuit or in synthesizing the
circuit.

I've noticed that in 8.1i leaving output ports undriven results in an
error
when you get to BitGen, while in 6.1i and earlier these nets were just
ripped out of the design in mapping.

Hi all, I want to use a small cricuit (written in verilog and was
designed using ISE 3) in an other project using ISE 8.1. the problem is
that under ISE 3 the circuit worked perfectly, and under ISE 8.1 the is
an error. why this occur ?