>Hi, I think it is, as you can see from table 21 on page 23 of DS099-3
>(Spartan3 datasheet), LVDS low input is (Vicm - 0.125), while LVDS high
>is (Vicm + 0.125), so the difference is 25mV.
>Marco
>
>
>
Funny, I read what you have above as 250 mV.
40 mV should work, at the chip, but leaves very little room for external
noise
sources. A very short run might work fine, but a long cable between
separate
pieces of equipment could easily pick up enough noise that is not perfectly
balanced and cause errors.
Jon
Reply by ●March 7, 20062006-03-07
Thanks all for your time,
I looked at the data sheet (didn't know where to look at, a search on
LVDS didn't help, so many tanks for the directions) and as far as I can
see its min 100mV and max 600mV..
Best
H aka N
Reply by Symon●March 7, 20062006-03-07
"Marco" <marco@marylon.com> wrote in message
news:1141730919.700121.50560@v46g2000cwv.googlegroups.com...
> Hi, I think it is, as you can see from table 21 on page 23 of DS099-3
> (Spartan3 datasheet), LVDS low input is (Vicm - 0.125), while LVDS high
> is (Vicm + 0.125), so the difference is 25mV.
> Marco
>
Marco,
You might want to read that again. You're reading the table headed 'Test
Methods for Timing Measurement at I/Os'. Perhaps the table 'Recommended
Operating Conditions for User I/Os Using Differential Signal Standards'
might be more applicable? And also, I suggest a little more practice at
arithmetic. Or typing. 250mV is what you were looking for? ;-)
HTH, Syms.
Reply by Symon●March 7, 20062006-03-07
<hakan.sakman@gmail.com> wrote in message
news:1141729977.923850.43780@e56g2000cwe.googlegroups.com...
> Hi,
>
> I want to findout the minimum accepted voltage difference for LVDS in
> Xilinx Spartan3 FPGAs. For example is 40mV acceptable?
>
> Many thanks for the help in advance..
>
> H aka N
>
Did you try looking in the datasheet? Search for Vid.
HTH, Syms.
Reply by Marco●March 7, 20062006-03-07
Sorry for the mistake, it's 250mV!
Reply by Marco●March 7, 20062006-03-07
Hi, I think it is, as you can see from table 21 on page 23 of DS099-3
(Spartan3 datasheet), LVDS low input is (Vicm - 0.125), while LVDS high
is (Vicm + 0.125), so the difference is 25mV.
Marco
Reply by ●March 7, 20062006-03-07
Hi,
I want to findout the minimum accepted voltage difference for LVDS in
Xilinx Spartan3 FPGAs. For example is 40mV acceptable?
Many thanks for the help in advance..
H aka N