In article <1141896195.726430.177200
@u72g2000cwu.googlegroups.com>, offname@gmail.com says...
[ ... ]
> reg [31:0] temp_count=0;
> reg direction=1;
In simulation, you're dealing with software, and
initialization like this works fine.
After synthesis, you're dealing with hardware. If you
want initialization to happen, you have to synthesize
hardware to do it.
That usually means an input signal to your circuit. When
it's asserted, you do initialization. When it's released,
your circuit starts normal operation.
--
Later,
Jerry.
The universe is a figment of its own imagination.
Reply by chronoer●March 9, 20062006-03-09
counter is indeed too large
after i reduced the counter
it worked as i thought
thank you very much
Reply by Arlet●March 9, 20062006-03-09
chronoer wrote:
> initial begin
> direction<=1'b1;
> temp_count<=0;
> end
initial blocks are also ignored for synthesis.
You can either refer to your synthesis tool manual to see how to
initialize registers, or you can add a 'reset' input signal and add
some logic to reset registers whenever the reset is asserted.
The first option only works once during configuration, the second one
will work whenever the reset is asserted.
In addition, you could also reduce the counter size to use the same
number of bits as your delay. This doesn't fix the problem, but will
provide a quicker recovery in case things ever go wrong.
Reply by chronoer●March 9, 20062006-03-09
this time i add some codes:
initial begin
direction<=1'b1;
temp_count<=0;
end
it can't solve this problem either
and i found the led[0] has a low level lightness continuously not
normal
it also took "few minutes" to shine the led
could you give some better codes?
thanks a lot
Reply by Arlet●March 9, 20062006-03-09
chronoer wrote:
> Dear all
> i write a simple test for led on altera cyclone board by jtag
> protocol
>
> such as following: led[0] will shine with some frequence
>
> reg [31:0] temp_count=0;
> reg direction=1;
>
> parameter delay=23'h600000;
> always @( posedge clock)begin
> if(direction==1)begin
> temp_count=temp_count+1'b1;
> LED[0]=1;
> if(temp_count>=delay) begin
> direction=0;
> end
> end
> if(direction==0) begin
> temp_count=temp_count-1'b1;
> LED[0]=0;
> if(!(temp_count>0)) begin
> direction=1;
> end
> end
> end
> it did work after "few minutes"
> why it took "few minutes" to perform well, after i bured code into
> fpga completely
> thanks for reply
>
> Sincerely Chronoer
Most likely your synthesis tool ignores the 'reg direction = 1'
initialization, and initializes it at zero instead. This results in
down count from 0 to delay. which takes ~4 billion clock cycles.
Completely unrelated, but you should also use '<=' instead of '='
Reply by chronoer●March 9, 20062006-03-09
Dear all
i write a simple test for led on altera cyclone board by jtag
protocol
such as following: led[0] will shine with some frequence
reg [31:0] temp_count=0;
reg direction=1;
parameter delay=23'h600000;
always @( posedge clock)begin
if(direction==1)begin
temp_count=temp_count+1'b1;
LED[0]=1;
if(temp_count>=delay) begin
direction=0;
end
end
if(direction==0) begin
temp_count=temp_count-1'b1;
LED[0]=0;
if(!(temp_count>0)) begin
direction=1;
end
end
end
it did work after "few minutes"
why it took "few minutes" to perform well, after i bured code into
fpga completely
thanks for reply
Sincerely Chronoer