I just set the output slew rate to slow (for all pins) in Xilinx ISE
"implement design properties" (considering the fact that its default
was on fast) and it became O.K. I don't know what you mean by clock IP
node?
Jim Granville wrote:
> Arash Majd wrote:
> > Hello Dear friends
> > Thanks for all your careful attentions.
> > I found the solutions. I have set the slew rate setting to slow instead
> > of fast. When I did this,The jitter came down to .05 UIpp.
> >
> > Arash Majd
>
> Good to hear you did not need a new PCB design :)
>   The fast/slow is not well explained in most data, as it also means
> HiDrive/LoDrive, and thus more ground bounce can come from Fast(HiDrive).
>   ie unless the last ns matters on long lines, use Slow...
>
>   Did you try fast only on the ClkOUT pin, and Hysteresis on/off on
> the clock IP node ?
> 
> -jg

Arash Majd wrote:
> Hello Dear friends
> Thanks for all your careful attentions.
> I found the solutions. I have set the slew rate setting to slow instead
> of fast. When I did this,The jitter came down to .05 UIpp.
> 
> Arash Majd

Good to hear you did not need a new PCB design :)
  The fast/slow is not well explained in most data, as it also means
HiDrive/LoDrive, and thus more ground bounce can come from Fast(HiDrive).
  ie unless the last ns matters on long lines, use Slow...

  Did you try fast only on the ClkOUT pin, and Hysteresis on/off on
the clock IP node ?

-jg

Hello Dear friends
Thanks for all your careful attentions.
I found the solutions. I have set the slew rate setting to slow instead
of fast. When I did this,The jitter came down to .05 UIpp.

Arash Majd

Arash Majd wrote:
> Hello Dear friends
> The board we have designed uses of XC2C256 in its center which
> distributes and switches between different signals in system. We use of
> a timing chip which derives the the output of the optical interface of
> our board. The output clock of the timing chip (named zl_1944_clk)
> which is very exact is 19.44 MHz which we have connected to the CPLD's
> GCK0 input pin and assigned this net to an output on one of the
> ordinary I/O pins to the  clock net of the driving ASIC of the optical
> interface. At this case he measured output jitter on the optical
> interface is approximately 0.12  UIpp and fluctuates unacceptedly
> between 0.08 and 0.15. But when the same signal (zl_1944_clk) is input
> from another input (I/O) port,  the output jitter decreases down to
> 0.05 UIpp. (maenwhile when we bypass the cpld in this net the output
> jitter is 0.07 and doesn't fluctuate that much.)
> Besides, when I get the fitter report of the xilinx ISE 6.1i, it says
> "global clock nets unused".( Although I have connected the zl_1944_clk
> net to GCK0 pin)
> I checked my project with ISE 7.1i, too and it did not work, too.
> I would be grateful if someone help me about this problem and he
> following questions.
>
>
> 1-Is there any point in using GCK0 pin ?
> 2-Should I use of timing constraints to make ISE to route my clock
> signal as desired.
>
> I am under pressure and i should deliver the product as soon as
> possible.
> 
> 
> thanks

Here's my guess:
You have a Zarlink low-jitter source for 19.44MHz and you are running
through a CPLD before attaching to the ASIC connected to the board's
optics.

Whenever you use an expensive chip to give you a low jitter clock, you
don't want to ruin it by running through a part with indeterminate
jitter. You've just destroyed your clock's known jitter range. The
output of the CPLD will be affected by nearby switching IO because the
IO buffers share power and ground lines and they all feed noise to
these lines on the chip. Most ASICs driving optics require a clock
source with known jitter and you don't have it.

I like the solutions you were given that bypass the CPLD altogether.

Jim Granville wrote:
> Arash Majd wrote:
>
> > Hello and thanks for your attention
> >
> > Data bus signals, address bus signals, Micro(MPC 860) 50MHz clock, some
> > other clocks like (retiming clocks, 19.44 Mhz clocks) are some of the
> > other signals routed in our CPLD. I can not change my pin assignment,
> > because the zl_1944_clk comes into CPLD only from only GCK0 pin.
>
> So you mean you have a pile of completed PCBs, and are after a
> 'SW only' solution ?
>
> > What I should do to make ISE consider zl_1944_clk as a global signal?
>
> Does the 19.44Mhz clock anything inside the CPLD ?
> If not, then it will not form a gCLK - but you could create a
> register for it to clock, and thus change the routing paths.
>
There is only two or three signal assignments.
for example :
CKREF0<=ZL_1944_CLK
CKREF1<=ZL_1944_CLK
How should I create a register for it ? you mean that I implement a
counter in my design?

> How far, physically, between the IN and OUT pins ?
>
The input pin(GCK0) belongs to functional block5 and the CKREF0 pin
(output pin) belongs to FB15. and the CKREF0 and the optical driver
module is nearly 10 cm far.

> Also, noise on Vcc/Gnd will aggravate this - PCB layers, decoupling ?
>
I am sure that the power planes are O.K and the decoupling capacitances
are proper, because when I input this signal from another input (by
wire ) the output jitter is O.K.


> What else happens to the 19.44Mhz ? - ie could you use a TinyLogic
> gate as Buffer/Switch, skipping the CPLD entirely - tiny logic devices
> will have very low jitter, as they have only one gate with its very-own
> supply rails.  No common mode inductance at all....
You mean that I change my PCB?


> 
> -jg

"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> 
wrote in message news:dusaos$gv9$1@sunnews.cern.ch...
> Hows about making the signal drive some flip-flops inside the device.
> Make sure that the output of the flip-flops gets used somewhere else it'll 
> all be optimised away.
> Oh, and I don't know your situation, but be careful about any unusual 
> functions that you may have inferred on the CLK0, I did some tests with an 
> XC95144XL a while ago:
> A clock in of 10MHz had a jitter of 70ps when it was directly output, that 
> rose to 150ps when combinational stages appeared before the output. (well, 
> in a simplified manner that's what I saw)
> Hope that helps.
> Ben

The 70ps and 150ps numbers are cleaner that what I expected but make good 
sense.  The 0.12 UI doesn't make sense at 19.44 MHz but does for 
significantly higher output rates slaved off the 19.44 MHz clock.

To the original poster or anyone else doing designs that have excessive 
constraints on jitter such as telecom systems and high speed/accuracy A/D 
converters, PLEASE design to provide the cleanest clock in the system to the 
stages that need the cleanest clock.

Generic logic with unrelated activity "close by" will cause jitter either at 
the input to the chip or coming back off the chip.  That's the nature of the 
beast.  A discrete buffer would have been a better way to achieve the 
required low jitter levels.

Arash Majd wrote:

> Hello and thanks for your attention
> 
> Data bus signals, address bus signals, Micro(MPC 860) 50MHz clock, some
> other clocks like (retiming clocks, 19.44 Mhz clocks) are some of the
> other signals routed in our CPLD. I can not change my pin assignment,
> because the zl_1944_clk comes into CPLD only from only GCK0 pin.

So you mean you have a pile of completed PCBs, and are after a
'SW only' solution ?

> What I should do to make ISE consider zl_1944_clk as a global signal?

Does the 19.44Mhz clock anything inside the CPLD ?
If not, then it will not form a gCLK - but you could create a
register for it to clock, and thus change the routing paths.

How far, physically, between the IN and OUT pins ?

Also, noise on Vcc/Gnd will aggravate this - PCB layers, decoupling ?

What else happens to the 19.44Mhz ? - ie could you use a TinyLogic
gate as Buffer/Switch, skipping the CPLD entirely - tiny logic devices 
will have very low jitter, as they have only one gate with its very-own 
supply rails.  No common mode inductance at all....

-jg

Hows about making the signal drive some flip-flops inside the device.
Make sure that the output of the flip-flops gets used somewhere else it'll 
all be optimised away.
Oh, and I don't know your situation, but be careful about any unusual 
functions that you may have inferred on the CLK0, I did some tests with an 
XC95144XL a while ago:
A clock in of 10MHz had a jitter of 70ps when it was directly output, that 
rose to 150ps when combinational stages appeared before the output. (well, 
in a simplified manner that's what I saw)
Hope that helps.
Ben

"Arash Majd" <arash_majd@ee.sharif.edu> wrote in message 
news:1141989340.207522.111170@z34g2000cwc.googlegroups.com...
> Hello and thanks for your attention
>
> Data bus signals, address bus signals, Micro(MPC 860) 50MHz clock, some
> other clocks like (retiming clocks, 19.44 Mhz clocks) are some of the
> other signals routed in our CPLD. I can not change my pin assignment,
> because the zl_1944_clk comes into CPLD only from only GCK0 pin.
> What I should do to make ISE consider zl_1944_clk as a global signal?
>
> (I would be grateful if  possible for you to provide me with a phone
> number to speak to you)
> 

Hello and thanks for your attention

Data bus signals, address bus signals, Micro(MPC 860) 50MHz clock, some
other clocks like (retiming clocks, 19.44 Mhz clocks) are some of the
other signals routed in our CPLD. I can not change my pin assignment,
because the zl_1944_clk comes into CPLD only from only GCK0 pin.
What I should do to make ISE consider zl_1944_clk as a global signal?

(I would be grateful if  possible for you to provide me with a phone
number to speak to you)

John_H wrote:
> "Jim Granville" <no.spam@designtools.co.nz> wrote in message 
> news:44108832$1@clear.net.nz...
> 
>>It sounds like you are using this as a simple buffer - in that case,
>>any pins can be used - select until you find the lowest jitter ones :)
> 
> 
> Since the clock is 19.44 MHz, the 51.44 ns period should show 0.05 UI of 
> jitter, much less 0.12 UI.
> 
> I would think much of the jitter problem is in an I/O with ridiculously low 
> drive or a mismatch in voltage levels that leaves the high logic level up to 
> a pull-up resister.
> 
> I would expect 2 ns at the outside for jitter in a noisy CPLD and would hope 
> for *much* less.
> 
> Anyone know if there would be benefit to driving the output MacroCell with a 
> TFF in DualEdge mode rather than routing the signal through to the buffer? 

  Probably not, as the jitter causes, as you suggest, as normally quasi 
analog effect ( slow rises, etc ). Once the signals are inside the
device, and digital, the damage is already done....

  The slower the edges, the more common mode impedances in GND and VCC 
matter.
  For this type of problem, I'd choose a 'quiet bank' for the buffer, 
and pins close to the GND pins, with few local aggressors.
The OP was a bit vague on what else was going on around this net ...

  -jg