On Fri, 07 Apr 2006 16:50:08 +0200, Gerhard Hoffmann
<dk4xp@freenet.de> wrote:

>On Wed, 22 Mar 2006 12:00:26 +1100, Allan Herriman <allanherriman@hotmail.com> wrote:
>
>>On 21 Mar 2006 09:08:21 -0800, "Alain" <no_spa2005@yahoo.fr> wrote:
>>
>>>Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf :
>>>"Payload compatible only"), so no hope for OTU-2 I think.
>>>We have to wait Virtex-5 family ?
>>
>>No.  That is unlikely to have sufficient jitter performance, due to
>>certain compromises that must be made when putting an MGT on an FPGA.
>>In particular, it's likely to use a ring oscillator rather than an LC
>>oscillator which would have better perfomance.
>
>Is jitter the only limitation? Most fiber optic transceivers (XFP & friends)
>have eye openers of their own and resynchronize everything anyway.

An XFP will have a JTF bandwidth in the order of 1MHz.  A SERDES will
have a JTF bandwidth of 1-2 orders of magnitude less than that, so
resynchronisation in the XFP doesn't solve all the jitter problems.

Regards,
Allan

I didn't see this info on Xilinx's site! Is it official?
On the last Virtex-4 datasheet (ds302) the speed grade -12x disapeared
but not the -11x!

mike_la_jolla wrote:
> The -11X speed grade is dead as of this week.  Do this some other way.

The -11X speed grade is dead as of this week.  Do this some other way.

On Wed, 22 Mar 2006 12:00:26 +1100, Allan Herriman <allanherriman@hotmail.com> wrote:

>On 21 Mar 2006 09:08:21 -0800, "Alain" <no_spa2005@yahoo.fr> wrote:
>
>>Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf :
>>"Payload compatible only"), so no hope for OTU-2 I think.
>>We have to wait Virtex-5 family ?
>
>No.  That is unlikely to have sufficient jitter performance, due to
>certain compromises that must be made when putting an MGT on an FPGA.
>In particular, it's likely to use a ring oscillator rather than an LC
>oscillator which would have better perfomance.

Is jitter the only limitation? Most fiber optic transceivers (XFP & friends)
have eye openers of their own and resynchronize everything anyway.

regards, Gerhard

I have seen that note as well, but I don't understand it.

Can someone explain what "Payload compatible only" means?

Alain wrote:
> Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf :
> "Payload compatible only"), so no hope for OTU-2 I think.
> We have to wait Virtex-5 family ?
> 

I have seen that note as well. Can someone explain what "Payload 
compatible only" means?

Alain wrote:
> Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf :
> "Payload compatible only"), so no hope for OTU-2 I think.
> We have to wait Virtex-5 family ?
> 

I have seen that note as well. Can someone explain what "Payload 
compatible only" means?

Alain wrote:
> Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf :
> "Payload compatible only"), so no hope for OTU-2 I think.
> We have to wait Virtex-5 family ?
> 

I have seen that note as well. Can someone explain what "Payload 
compatible only" means?

On 23 Mar 2006 06:22:37 -0800, "GaLaKtIkUs&#4294967295;" <taileb.mehdi@gmail.com>
wrote:

>Can you indicate me such a SERDES. It's perfect if its output is
>64bits. Also it shoulden't do FEC stuff. FEC is planned to be done on
>FPGA.

Most 10Gb/s SERDES parts seem to have 16 bit interfaces, probably
because there's common interface definition called SFI-4 that has 16
LVDS pairs clocked at 622-670MHz.

Xilinx has an app note called XAPP 622 that describes how to implement
such an interface on an FPGA.

Did you use Google?  You would have found SERDES manufacturers such as
PMC, AMCC, Broadcom, etc.

>Thnaks in advance
>Mehdi

Thanks for the top-post!

>
>Allan Herriman wrote:
>> On 21 Mar 2006 09:08:21 -0800, "Alain" <no_spa2005@yahoo.fr> wrote:
>>
>> >Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf :
>> >"Payload compatible only"), so no hope for OTU-2 I think.
>> >We have to wait Virtex-5 family ?
>>
>> No.  That is unlikely to have sufficient jitter performance, due to
>> certain compromises that must be made when putting an MGT on an FPGA.
>> In particular, it's likely to use a ring oscillator rather than an LC
>> oscillator which would have better perfomance.
>>
>> Use an external SERDES designed for G.707 / G.709 work.
>>
>> Note that (before they discontinued it) Xilinx's standalone SERDES
>> didn't meet the SONET jitter requirements either, so getting these
>> things to work is clearly not a trivial task.
>> 
>> Regards,
>> Allan

Can you indicate me such a SERDES. It's perfect if its output is
64bits. Also it shoulden't do FEC stuff. FEC is planned to be done on
FPGA.

Thnaks in advance
Mehdi

Allan Herriman wrote:
> On 21 Mar 2006 09:08:21 -0800, "Alain" <no_spa2005@yahoo.fr> wrote:
>
> >Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf :
> >"Payload compatible only"), so no hope for OTU-2 I think.
> >We have to wait Virtex-5 family ?
>
> No.  That is unlikely to have sufficient jitter performance, due to
> certain compromises that must be made when putting an MGT on an FPGA.
> In particular, it's likely to use a ring oscillator rather than an LC
> oscillator which would have better perfomance.
>
> Use an external SERDES designed for G.707 / G.709 work.
>
> Note that (before they discontinued it) Xilinx's standalone SERDES
> didn't meet the SONET jitter requirements either, so getting these
> things to work is clearly not a trivial task.
> 
> Regards,
> Allan