On Wednesday, September 25, 2019 at 11:16:40 PM UTC-4, Weng Tianxiang wrote:
> On Wednesday, September 25, 2019 at 3:22:53 PM UTC-7, Rick C wrote:
> > On Wednesday, September 25, 2019 at 5:53:38 PM UTC-4, Weng Tianxiang wrote:
> 
> For 2 writes on the same cycle to an array now you have to refer to a special library either from Xilink or Altera. 
> 
That is incorrect.  Since this is your premise for your new if_2 statement, and it is incorrect you should go back to rethinking the supposed problem.

> Even though referring a library is not difficult coding problem, but your code has to change if you move chip provider from one to another.
> 
No you don't.

> 
> Anywhere an if statement can be used an if_2 statement can be used!
> 
Not only that, but the if statement can be used whenever the if_2 statement can be used, there is no need for if_2.

> With "if_2" introduction you don't have to remember any library from which company.
No need to remember if_2 either.  But don't worry, Google will remember.

Kevin Jennings

On Wednesday, September 25, 2019 at 9:30:11 PM UTC-7, Rick C wrote:
> On Wednesday, September 25, 2019 at 11:16:40 PM UTC-4, Weng Tianxiang wrote:
> > On Wednesday, September 25, 2019 at 3:22:53 PM UTC-7, Rick C wrote:
> > > On Wednesday, September 25, 2019 at 5:53:38 PM UTC-4, Weng Tianxiang wrote:
> > > > Hi,
> > > > In my opinion, using a 2-write port memory is a mature technique and its implementation in any chip is never a secret. Hardware designers in HDL often use 2-write port memory in their applications.
> > > > 
> > > > To relieve hardware designers from repeatedly writing complex code for a 2-write port memory, I suggest here for full HDL grammar spectrum to introduce a new keyword "if_2" and new "if_2" statement, specifying a new if statement which has everything same as an if statement, but it specifies a second write to an array. Here is a code example on how to introduce such statement:
> > > > 
> > > > p1: process(CLK) is
> > > > begin
> > > >   if CLK'event and CLK = '1' then
> > > >     if C1 then
> > > >       An_Array(a) <= D1; -- it is first write to array An_Array
> > > >     end if;
> > > > 
> > > > -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process.
> > > > 
> > > >     if_2 C2 then
> > > >       An_Array(b) <= D2; -- it is a second write to array An_Array
> > > >     end if;
> > > >   end if;
> > > > end process;
> > > > 
> > > > If a 2nd write to an array does not need any condition, the statement can be written as:
> > > > 
> > > >     if_2 '1' then
> > > >       An_Array(b) <= D2; -- it is a second write without any condition
> > > >     end if;
> > > > 
> > > > Using the new suggested keyword "if_2" in HDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chips.
> > > > 
> > > > Weng
> > > 
> > > Can you give an example of the code this would replace???  I don't remember two port memory code being all that complex.  
> > > 
> > > -- 
> > > 
> > >   Rick C.
> > > 
> > >   - Get 2,000 miles of free Supercharging
> > >   - Tesla referral code - https://ts.la/richard11209
> > 
> > For 2 writes on the same cycle to an array now you have to refer to a special library either from Xilink or Altera. 
> 
> I would suggest you spend more time researching this.  I had no trouble finding info on inferring dual write port RAMs with Xilinx tools. 
> 
> http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/xst_v6s6.pdf (page 250)
> 
> 
> > Even though referring&nbsp;a library is not difficult coding problem, but your code has to change if you move chip provider from one to another.
> > 
> > With introduction of "if_2" concept you never have to refer to any library, and it would become normal and simple as addition of A and B!
> > 
> > Here is a more example:
> > p1: process(CLK) is
> > begin
> >   if CLK'event and CLK = '1' then
> >     if C1 thenAn_Array(a) <= D1; -- it is first write to array An_Array
> >       if_2 C2 then
> >         An_Array(b) <= D2; -- it is a second write to An_Array
> >       end if;
> >     end if;
> >   end if;
> > end process;
> > 
> > Anywhere an if statement can be used an if_2 statement can be used!
> > 
> > With "if_2" introduction you don't have to remember any library from which company.
> 
> I think you will find both a great deal of resistance since the general construct of VHDL is not to provide specific features in the language to specify hardware, rather to describe behavior and let the tools infer appropriate hardware corresponding to the target technology.  
> 
> I would also point out your code is not appropriate for a dual port RAM since the second port can only be written to when the first port is being written to.  Shouldn't they both be independent as was the case in your other examples in the other thread? 
> 
> -- 
> 
>   Rick C.
> 
>   + Get 2,000 miles of free Supercharging
>   + Tesla referral code - https://ts.la/richard11209

Rick,

I just list a code snippet that suggests if statement and if_2 statement can be mixed, not a code error. 

Weng

On Wednesday, September 25, 2019 at 11:16:40 PM UTC-4, Weng Tianxiang wrote:
> On Wednesday, September 25, 2019 at 3:22:53 PM UTC-7, Rick C wrote:
> > On Wednesday, September 25, 2019 at 5:53:38 PM UTC-4, Weng Tianxiang wrote:
> > > Hi,
> > > In my opinion, using a 2-write port memory is a mature technique and its implementation in any chip is never a secret. Hardware designers in HDL often use 2-write port memory in their applications.
> > > 
> > > To relieve hardware designers from repeatedly writing complex code for a 2-write port memory, I suggest here for full HDL grammar spectrum to introduce a new keyword "if_2" and new "if_2" statement, specifying a new if statement which has everything same as an if statement, but it specifies a second write to an array. Here is a code example on how to introduce such statement:
> > > 
> > > p1: process(CLK) is
> > > begin
> > >   if CLK'event and CLK = '1' then
> > >     if C1 then
> > >       An_Array(a) <= D1; -- it is first write to array An_Array
> > >     end if;
> > > 
> > > -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process.
> > > 
> > >     if_2 C2 then
> > >       An_Array(b) <= D2; -- it is a second write to array An_Array
> > >     end if;
> > >   end if;
> > > end process;
> > > 
> > > If a 2nd write to an array does not need any condition, the statement can be written as:
> > > 
> > >     if_2 '1' then
> > >       An_Array(b) <= D2; -- it is a second write without any condition
> > >     end if;
> > > 
> > > Using the new suggested keyword "if_2" in HDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chips.
> > > 
> > > Weng
> > 
> > Can you give an example of the code this would replace???  I don't remember two port memory code being all that complex.  
> > 
> > -- 
> > 
> >   Rick C.
> > 
> >   - Get 2,000 miles of free Supercharging
> >   - Tesla referral code - https://ts.la/richard11209
> 
> For 2 writes on the same cycle to an array now you have to refer to a special library either from Xilink or Altera. 

I would suggest you spend more time researching this.  I had no trouble finding info on inferring dual write port RAMs with Xilinx tools. 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/xst_v6s6.pdf (page 250)


> Even though referring&nbsp;a library is not difficult coding problem, but your code has to change if you move chip provider from one to another.
> 
> With introduction of "if_2" concept you never have to refer to any library, and it would become normal and simple as addition of A and B!
> 
> Here is a more example:
> p1: process(CLK) is
> begin
>   if CLK'event and CLK = '1' then
>     if C1 thenAn_Array(a) <= D1; -- it is first write to array An_Array
>       if_2 C2 then
>         An_Array(b) <= D2; -- it is a second write to An_Array
>       end if;
>     end if;
>   end if;
> end process;
> 
> Anywhere an if statement can be used an if_2 statement can be used!
> 
> With "if_2" introduction you don't have to remember any library from which company.

I think you will find both a great deal of resistance since the general construct of VHDL is not to provide specific features in the language to specify hardware, rather to describe behavior and let the tools infer appropriate hardware corresponding to the target technology.  

I would also point out your code is not appropriate for a dual port RAM since the second port can only be written to when the first port is being written to.  Shouldn't they both be independent as was the case in your other examples in the other thread? 

-- 

  Rick C.

  + Get 2,000 miles of free Supercharging
  + Tesla referral code - https://ts.la/richard11209

On Wednesday, September 25, 2019 at 3:22:53 PM UTC-7, Rick C wrote:
> On Wednesday, September 25, 2019 at 5:53:38 PM UTC-4, Weng Tianxiang wrote:
> > Hi,
> > In my opinion, using a 2-write port memory is a mature technique and its implementation in any chip is never a secret. Hardware designers in HDL often use 2-write port memory in their applications.
> > 
> > To relieve hardware designers from repeatedly writing complex code for a 2-write port memory, I suggest here for full HDL grammar spectrum to introduce a new keyword "if_2" and new "if_2" statement, specifying a new if statement which has everything same as an if statement, but it specifies a second write to an array. Here is a code example on how to introduce such statement:
> > 
> > p1: process(CLK) is
> > begin
> >   if CLK'event and CLK = '1' then
> >     if C1 then
> >       An_Array(a) <= D1; -- it is first write to array An_Array
> >     end if;
> > 
> > -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process.
> > 
> >     if_2 C2 then
> >       An_Array(b) <= D2; -- it is a second write to array An_Array
> >     end if;
> >   end if;
> > end process;
> > 
> > If a 2nd write to an array does not need any condition, the statement can be written as:
> > 
> >     if_2 '1' then
> >       An_Array(b) <= D2; -- it is a second write without any condition
> >     end if;
> > 
> > Using the new suggested keyword "if_2" in HDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chips.
> > 
> > Weng
> 
> Can you give an example of the code this would replace???  I don't remember two port memory code being all that complex.  
> 
> -- 
> 
>   Rick C.
> 
>   - Get 2,000 miles of free Supercharging
>   - Tesla referral code - https://ts.la/richard11209

For 2 writes on the same cycle to an array now you have to refer to a special library either from Xilink or Altera. 

Even though referring&nbsp;a library is not difficult coding problem, but your code has to change if you move chip provider from one to another.

With introduction of "if_2" concept you never have to refer to any library, and it would become normal and simple as addition of A and B!

Here is a more example:
p1: process(CLK) is
begin
  if CLK'event and CLK = '1' then
    if C1 thenAn_Array(a) <= D1; -- it is first write to array An_Array
      if_2 C2 then
        An_Array(b) <= D2; -- it is a second write to An_Array
      end if;
    end if;
  end if;
end process;

Anywhere an if statement can be used an if_2 statement can be used!

With "if_2" introduction you don't have to remember any library from which company.

On Wednesday, September 25, 2019 at 5:53:38 PM UTC-4, Weng Tianxiang wrote:
> Hi,
> In my opinion, using a 2-write port memory is a mature technique and its implementation in any chip is never a secret. Hardware designers in HDL often use 2-write port memory in their applications.
> 
> To relieve hardware designers from repeatedly writing complex code for a 2-write port memory, I suggest here for full HDL grammar spectrum to introduce a new keyword "if_2" and new "if_2" statement, specifying a new if statement which has everything same as an if statement, but it specifies a second write to an array. Here is a code example on how to introduce such statement:
> 
> p1: process(CLK) is
> begin
>   if CLK'event and CLK = '1' then
>     if C1 then
>       An_Array(a) <= D1; -- it is first write to array An_Array
>     end if;
> 
> -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process.
> 
>     if_2 C2 then
>       An_Array(b) <= D2; -- it is a second write to array An_Array
>     end if;
>   end if;
> end process;
> 
> If a 2nd write to an array does not need any condition, the statement can be written as:
> 
>     if_2 '1' then
>       An_Array(b) <= D2; -- it is a second write without any condition
>     end if;
> 
> Using the new suggested keyword "if_2" in HDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chips.
> 
> Weng

Can you give an example of the code this would replace???  I don't remember two port memory code being all that complex.  

-- 

  Rick C.

  - Get 2,000 miles of free Supercharging
  - Tesla referral code - https://ts.la/richard11209

Hi,
In my opinion, using a 2-write port memory is a mature technique and its implementation in any chip is never a secret. Hardware designers in HDL often use 2-write port memory in their applications.

To relieve hardware designers from repeatedly writing complex code for a 2-write port memory, I suggest here for full HDL grammar spectrum to introduce a new keyword "if_2" and new "if_2" statement, specifying a new if statement which has everything same as an if statement, but it specifies a second write to an array. Here is a code example on how to introduce such statement:

p1: process(CLK) is
begin
  if CLK'event and CLK = '1' then
    if C1 then
      An_Array(a) <= D1; -- it is first write to array An_Array
    end if;

-- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process.

    if_2 C2 then
      An_Array(b) <= D2; -- it is a second write to array An_Array
    end if;
  end if;
end process;

If a 2nd write to an array does not need any condition, the statement can be written as:

    if_2 '1' then
      An_Array(b) <= D2; -- it is a second write without any condition
    end if;

Using the new suggested keyword "if_2" in HDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chips.

Weng