> In article <qqb5mf$e1f$1@dont-email.me>,
> David Brown <david.brown@hesbynett.no> wrote:
>> On 09/11/2019 00:12, Rick C wrote:
>>> On Friday, November 8, 2019 at 5:48:04 PM UTC-5, Stef wrote:
>>>> On 2019-11-08 Rick C wrote in comp.arch.fpga:
>>>>> On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
>>>>>>
>>>>>> Please consider this a PHB type question. I don't do FPGA development
>>>>>> myself, past whiteboarding.
>>>>>
>>>>> Anyone know what a "PHB type question" is?
>>>>
>>>> https://dilbert.com/search_results?terms=phb
>>>
>>> Yeah, someone explained in the other group. A bit obscure, methinks.
>>>
>>
>> Nah. I get suspicious of any engineer who doesn't know the term PHB!
>>
>> It's like not understanding the term SEP.
>
> I had to think a bit to come up with PHB, but I got it. I've no idea
> what SEP is.
"Somebody else's problem". It's a term from Douglas Adams:
"""
An SEP is something we can't see, or don't see, or our brain doesn't let
us see, because we think that it's somebody else's problem. That’s what
SEP means. Somebody Else’s Problem. The brain just edits it out, it's
like a blind spot.
"""
<https://en.wikipedia.org/wiki/Somebody_else's_problem>
It is very useful in all kinds of engineering, for helping focus on the
task /you/ have to do instead of everyone else's tasks.
>
> But then I'm acronymn dumb (and too lazy to try and google it right
> now.)
You need to swat up on your TLA's :-)
>
> (I've got a feeling a "whoosh" at my expense is incoming...)
>
> --Mark
>
>
>
>
Reply by gtwrek●November 11, 20192019-11-11
In article <qqb5mf$e1f$1@dont-email.me>,
David Brown <david.brown@hesbynett.no> wrote:
>On 09/11/2019 00:12, Rick C wrote:
>> On Friday, November 8, 2019 at 5:48:04 PM UTC-5, Stef wrote:
>>> On 2019-11-08 Rick C wrote in comp.arch.fpga:
>>>> On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
>>>>>
>>>>> Please consider this a PHB type question. I don't do FPGA development
>>>>> myself, past whiteboarding.
>>>>
>>>> Anyone know what a "PHB type question" is?
>>>
>>> https://dilbert.com/search_results?terms=phb
>>
>> Yeah, someone explained in the other group. A bit obscure, methinks.
>>
>
>Nah. I get suspicious of any engineer who doesn't know the term PHB!
>
>It's like not understanding the term SEP.
I had to think a bit to come up with PHB, but I got it. I've no idea
what SEP is.
But then I'm acronymn dumb (and too lazy to try and google it right
now.)
(I've got a feeling a "whoosh" at my expense is incoming...)
--Mark
Reply by David Brown●November 11, 20192019-11-11
On 09/11/2019 00:12, Rick C wrote:
> On Friday, November 8, 2019 at 5:48:04 PM UTC-5, Stef wrote:
>> On 2019-11-08 Rick C wrote in comp.arch.fpga:
>>> On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
>>>>
>>>> Please consider this a PHB type question. I don't do FPGA development
>>>> myself, past whiteboarding.
>>>
>>> Anyone know what a "PHB type question" is?
>>
>> https://dilbert.com/search_results?terms=phb
>
> Yeah, someone explained in the other group. A bit obscure, methinks.
>
Nah. I get suspicious of any engineer who doesn't know the term PHB!
It's like not understanding the term SEP.
Reply by dalai lamah●November 10, 20192019-11-10
Un bel giorno John Larkin digit�:
> We're planning a new universal boot loader for a family of ST
> processors. The uP would host the loader in a bit of local flash and
> read an outboard serial flash to get the specific application code and
> one or more FPGA configurations.
>
> So, how many config bits might there be for a modern mid-range FPGA
> doing a moderately complex application?
>
> I think we could enable compression too.
>
> Please consider this a PHB type question. I don't do FPGA development
> myself, past whiteboarding.
My PHB answer would be 32 Mbit.
However, "mid-range" FPGA is a very broad definition. These days I would
call mid-range something like the Spartan 7 family, but probably someone
could argue that it is already low-range. So you could choose 32 Mbit
(which is the maximum bitstream size required for the Spartan-7 and for a
mid-range Artix 7) or go a little further to accomodate also the mid-range
Kintex-7. See table 1-1:
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
--
Fletto i muscoli e sono nel vuoto.
Reply by ●November 9, 20192019-11-09
On Sat, 9 Nov 2019 11:15:56 +0000, TTman <kraken.sankey@gmail.com>
wrote:
>On 09/11/2019 09:49, Michael Kellett wrote:
>> On 08/11/2019 19:08, John Larkin wrote:
>>>
>>>
>>> We're planning a new universal boot loader for a family of ST
>>> processors. The uP would host the loader in a bit of local flash and
>>> read an outboard serial flash to get the specific application code and
>>> one or more FPGA configurations.
>>>
>>> So, how many config bits might there be for a modern mid-range FPGA
>>> doing a moderately complex application?
>>>
>>> I think we could enable compression too.
>>>
>>> Please consider this a PHB type question. I don't do FPGA development
>>> myself, past whiteboarding.
>>>
>> From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039.
>>
>> LFE5-45 - 8.86Mb
>>
>>
>> From Xilinx UG470
>> Xilinx Artix 35T and 50T need the same 17.536 Mb
>>
>> MK
>Why complicate things with memory soooo cheap ??? Just store raw data...
> On 08/11/2019 19:08, John Larkin wrote:
>>
>>
>> We're planning a new universal boot loader for a family of ST
>> processors. The uP would host the loader in a bit of local flash and
>> read an outboard serial flash to get the specific application code and
>> one or more FPGA configurations.
>>
>> So, how many config bits might there be for a modern mid-range FPGA
>> doing a moderately complex application?
>>
>> I think we could enable compression too.
>>
>> Please consider this a PHB type question. I don't do FPGA development
>> myself, past whiteboarding.
>>
> From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039.
>
> LFE5-45 - 8.86Mb
>
>
> From Xilinx UG470
> Xilinx Artix 35T and 50T need the same 17.536 Mb
>
> MK
Why complicate things with memory soooo cheap ??? Just store raw data...
Reply by Michael Kellett●November 9, 20192019-11-09
On 08/11/2019 19:08, John Larkin wrote:
>
>
> We're planning a new universal boot loader for a family of ST
> processors. The uP would host the loader in a bit of local flash and
> read an outboard serial flash to get the specific application code and
> one or more FPGA configurations.
>
> So, how many config bits might there be for a modern mid-range FPGA
> doing a moderately complex application?
>
> I think we could enable compression too.
>
> Please consider this a PHB type question. I don't do FPGA development
> myself, past whiteboarding.
>
From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039.
LFE5-45 - 8.86Mb
From Xilinx UG470
Xilinx Artix 35T and 50T need the same 17.536 Mb
MK
Reply by Rick C●November 8, 20192019-11-08
On Friday, November 8, 2019 at 5:48:04 PM UTC-5, Stef wrote:
> On 2019-11-08 Rick C wrote in comp.arch.fpga:
> > On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
> >>
> >> Please consider this a PHB type question. I don't do FPGA development
> >> myself, past whiteboarding.
> >
> > Anyone know what a "PHB type question" is?
>
> https://dilbert.com/search_results?terms=phb
Yeah, someone explained in the other group. A bit obscure, methinks.
--
Rick C.
+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
Reply by Stef●November 8, 20192019-11-08
On 2019-11-08 Rick C wrote in comp.arch.fpga:
> On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
>>
>> Please consider this a PHB type question. I don't do FPGA development
>> myself, past whiteboarding.
>
> Anyone know what a "PHB type question" is?
https://dilbert.com/search_results?terms=phb
--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)
Corry's Law:
Paper is always strongest at the perforations.
Reply by ●November 8, 20192019-11-08
On Friday, November 8, 2019 at 1:09:04 PM UTC-6, John Larkin wrote:
> We're planning a new universal boot loader for a family of ST
> processors. The uP would host the loader in a bit of local flash and
> read an outboard serial flash to get the specific application code and
> one or more FPGA configurations.
>
> So, how many config bits might there be for a modern mid-range FPGA
> doing a moderately complex application?
>
> I think we could enable compression too.
>
> Please consider this a PHB type question. I don't do FPGA development
> myself, past whiteboarding.
>
> --
>
> John Larkin Highland Technology, Inc
> picosecond timing precision measurement
>
> jlarkin att highlandtechnology dott com
> http://www.highlandtechnology.com
There's a general trend of about 60-80 bits per LUT input (can go higher).
4LUT has ~4-6 inputs, 6LUT or ALM 6-8 inputs. Count the number of LUTs in the part and multiply. Some go as high as 400M+ configuration bits.
Jim Brakefield