Reply by Kevin Neilson●September 17, 20202020-09-17
On Wednesday, September 16, 2020 at 7:18:29 PM UTC-6, Kevin Simonson wrote:
> I've got a Verilog function that I'd like to behave slightly differently depending on the value of a boolean argument, an argument whose value can be either (true) or (false). I tried:
> [code]
> module sid ();
>
> function integer execOp;
> input integer left;
> input integer right;
> input boolean add;
> begin
> execOp = add ? left + right : left * right;
> end
> endfunction
>
> endmodule
> [/code]
> Then when I use Icarus to simulate it I get:
> [code]
> D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid.out sid.sv
> sid.sv:6: syntax error
> sid.sv:3: error: Syntax error defining function.
>
> D:\Hf\Verilog\Unpacked\Common>
> [/code]
> Line 6 is the line where I declare variable (add). Is there a way to pass a boolean argument to a function, or am I going to have to declare an (enum) that has values (true) and (false)?
There is no "Boolean" type in Verilog, as far as I know. The default type is a 1-bit register that is fairly equivalent. If you just delete the word "boolean" from your example, it should work.
Reply by Kevin Simonson●September 16, 20202020-09-16
I've got a Verilog function that I'd like to behave slightly differently depending on the value of a boolean argument, an argument whose value can be either (true) or (false). I tried:
[code]
module sid ();
function integer execOp;
input integer left;
input integer right;
input boolean add;
begin
execOp = add ? left + right : left * right;
end
endfunction
endmodule
[/code]
Then when I use Icarus to simulate it I get:
[code]
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid.out sid.sv
sid.sv:6: syntax error
sid.sv:3: error: Syntax error defining function.
D:\Hf\Verilog\Unpacked\Common>
[/code]
Line 6 is the line where I declare variable (add). Is there a way to pass a boolean argument to a function, or am I going to have to declare an (enum) that has values (true) and (false)?