Reply by Kevin Simonson●September 28, 20202020-09-28
Gtwrek (Mark): "Like another poster indicated - you're coding at a very low level. Instatiating 'xor2' primitives and the like is quite low level. Just inline the expression using the verilog '^', '|', '&', etc operators." What's wrong with writing Verilog at a low level? If someone has a feel for how her/his design should work at a low level, is there something wrong with coding it at that level? If so, what is wrong with it?
"Change your generate case() to a procedural case()." What exactly is a procedural case, and how can I find out about it?
Reply by gtwrek●September 25, 20202020-09-25
In article <071797c0-bfc0-4df1-b23e-f1519230330en@googlegroups.com>,
Kevin Simonson <kvnsmnsn@hotmail.com> wrote:
Your problem now is the generate case() statements. Generate case()
statements agruments DO need to be parameters. (I know I told you to
change it from a localparm to a variable - but I missed the generate case()
usage) However, I still don't think you should make these parameters.
Like another poster indicated - you're coding at a very low level.
Instatiating "xor2" primitives and the like is quite low level. Just
inline the expression using the verilog "^", "|", "&", etc operators.
Change your generate case() to a procedural case().
Another comment on style. Your function should really not be both
sampling, and manipulating non-local variables. Write your function
with a stable API that passes in the neccesary arguments, and returns
the neccesary outputs. Manipulating global variables, makes the
function call pretty purposeless.
There's no reason at all for it to be a function if it's
just manipulating global variables. Just move it down to the procedural
block if you don't want to solidify the API. Or put it in it's own
procedural block. Change the function to:
always @*
begin
//function contents that manipulate ndTypes[];
end
Regards,
Mark
Reply by Kevin Simonson●September 25, 20202020-09-25
D:\Hf\Verilog\Unpacked\Src\Common>\Icarus\bin\iverilog -g2009 -o neilson.vvp neilson.sv
neilson.sv:84: error: Unable to bind parameter `ndTypes[ix]' in `neilson.$gen1[1]'
neilson.sv:84: error: Cannot evaluate genvar case expression: ndTypes[ix]
2 error(s) during elaboration.
D:\Hf\Verilog\Unpacked\Src\Common>
Reply by Kevin Simonson●September 25, 20202020-09-25
Reply by Kevin Simonson●September 25, 20202020-09-25
Okay, I got rid of (struct) type (node) and now just have four arrays, (ndTypes), (inLows), (inHighs), and (outs). Then I used Icarus to simulate it, and only got one error message. Any idea how to get rid of that one error message? As before, the next post I make will be of my "neilson.sv" Verilog file, and the post after that will be the results of my attempt to simulate it.
Reply by gtwrek●September 24, 20202020-09-24
In article <rkibc5$jl0$1@dont-email.me>, gtwrek <gtwrek@sonic.net> wrote:
>In article <949f0dc7-6333-4b8e-b631-c4c82b825b04n@googlegroups.com>,
>Kevin Simonson <kvnsmnsn@hotmail.com> wrote:
>>localparam node nodes [ nmNodes:1];
>>localparam integer bases [ nmLevels:0];
>
>Going to break feedback down into parts...
>
>A localparam without an assignment makes no sense, and is likely a
>syntax error. Did you mean for these to be variables instead of
>localparams?
Briefly reading through the rest of the code, and how you're using/manipulating
"nodes" and "bases" - I think this is the root cause of your troubles.
Just try and make these variables instead of localparams. I don't think
there's any reason why they must be localparams.
Regards,
Mark
Reply by gtwrek●September 24, 20202020-09-24
In article <949f0dc7-6333-4b8e-b631-c4c82b825b04n@googlegroups.com>,
Kevin Simonson <kvnsmnsn@hotmail.com> wrote:
Going to break feedback down into parts...
A localparam without an assignment makes no sense, and is likely a
syntax error. Did you mean for these to be variables instead of
localparams?
Regards,
Mark
Reply by Kevin Neilson●September 23, 20202020-09-23
On Wednesday, September 23, 2020 at 4:45:55 PM UTC-6, Kevin Simonson wrote:
I have a few comments:
- You probably don't want to instantiate primitives like xor2. Maybe this =
is some idea you got from the Palnitkar book. The old books are more geare=
d toward circuit modeling, not circuit synthesis. You want "RTL" code, not=
"structural" code (in which you instantiate gates instead of inferring the=
m). To xor something, use the xor operator: result =3D a ^ b; To NAND so=
mething: result =3D ~(a & b);
- You are using a lot of "tricky" code, like structures, which are from Ver=
ilog-2009 (aka SystemVerilog). Many synthesizers aren't going to like this=
. I don't know about Icarus, but since it's free, I'd be wary. Synthesis =
tools are not great. It's not like a C compiler, where as long as your C i=
s legal, it's going to compile. Your "initial" blocks, functions, and stru=
ctures might not synthesize.
- You don't have the "generate" keyword before "for (ix ...". That might w=
ork in some tools, but I think it might be required by a strict interpretat=
ion. But you really shouldn't have a generate block anyway, because you re=
ally want RTL code and no gate primitives.
Reply by Kevin Simonson●September 23, 20202020-09-23
D:\Hf\Verilog\Unpacked\Src\Common>\Icarus\bin\iverilog -g2009 -o forMark.vvp forMark.sv
forMark.sv:19: sorry: cannot currently create a parameter of type 'node' which was defined at: forMark.sv:8.
forMark.sv:19: syntax error
forMark.sv:19: error: syntax error localparam list.
forMark.sv:20: syntax error
forMark.sv:20: error: syntax error localparam list.
forMark.sv:83: sorry: cannot currently create a parameter of type 'node' which was defined at: forMark.sv:8.
D:\Hf\Verilog\Unpacked\Src\Common>
Reply by Kevin Simonson●September 23, 20202020-09-23