Prakash wrote:
> Thanks, I think that , since Iam trying to program by USB Jtag, the
> warning I got is harmless and in my case its correctly assigned
> (startupclk=jtagclk).
> I didnt get an answer for, whether I need to integrate JTAG controller
> in logic, assign the TMS, TCK...pins or controller is hard coded, and
> no need to concern in my logic (probably second is right).
yes, it's a hard block, for configuration you dont't have to do anything 
it will be there for you,
  however you can hook it to your design, if you wish, to 
triger/debug/scan different parts of your logic.

Aurash
>  
> Prakash
> 

Thanks, I think that , since Iam trying to program by USB Jtag, the
warning I got is harmless and in my case its correctly assigned
(startupclk=jtagclk).
I didnt get an answer for, whether I need to integrate JTAG controller
in logic, assign the TMS, TCK...pins or controller is hard coded, and
no need to concern in my logic (probably second is right).
 
Prakash

Prakash wrote:
> Hi,
> Iam trying to download opensource processor in xilinx dev. board
> XUPV2P. I'm not using any of the features like (Power PC/ controllers)
> which are inbuilt / xilinx prop.
> Now I've a doubt If suppose I configure my bit file thro' USB Jtag
> interface, should my logic (to be downloaded) contain the JTAG
> controller also, or the controller is hard coded in the chip.
> 
> I get a warning while generating programming file in ISE,
> WARNING:Bitgen:244 - The IEEE1532 option implies that JTAG
> configuration will be
>    used. Using a StartupClk setting other than JtagClk could prevent
> proper
>    device startup.
> Please help esp. the second part of warning,
> Prakash
> 

when you generate the bitstream for JTAG programming, you need to check 
an option startupclk=jtagclk, otherwise (slave serial, or other non JTAG 
config) you need to have startupclk=cclk or startupclk=userclk)
what this means? after configuration (and during configuration) a state 
machine will take care of the start-up of your design, ie. releasing the 
global reset, releasing the global tristate for the IOs, assertin DONE 
pin etc. This option in the bitstream generation will "tell" to the fpga 
the source of clk for this state machine (this information is embedded 
into the bitstream file) when impact will program the fpga, impact knows 
the interface you choose and is checking against the bistream do see is 
the startup-clk option makes sense for the chosen programing interface.

Aurash

Hi,
Iam trying to download opensource processor in xilinx dev. board
XUPV2P. I'm not using any of the features like (Power PC/ controllers)
which are inbuilt / xilinx prop.
Now I've a doubt If suppose I configure my bit file thro' USB Jtag
interface, should my logic (to be downloaded) contain the JTAG
controller also, or the controller is hard coded in the chip.

I get a warning while generating programming file in ISE,
WARNING:Bitgen:244 - The IEEE1532 option implies that JTAG
configuration will be
   used. Using a StartupClk setting other than JtagClk could prevent
proper
   device startup.
Please help esp. the second part of warning,
Prakash