Hi Krysztof,

    The connections described in your post are not possible with the Stratix
architecture.

- Subroto Datta
Altera Corp.

"Krzysztof Szczepanski" <kszczepa@poczta.wp.pl> wrote in message
news:bp2sl9$s60$1@korweta.task.gda.pl...
> Hello,
>
> I have a problem with Stratix's PLLs.
> I want to feed input of Enhanced PLL from Fast PLL and Enhanced PLL form
> Enhanced PLL.
>
> CLK input -> Fast PLL     -> Enhanced PLL -> PLL output
>                                          -> other logic
>  or
> CLK input -> Enhanced PLL    -> Enhanced PLL -> PLL output
>                                                  -> other logic
>
> Is this two configuration possible to achieve in EP1S25 device?
>
> Quartus 3 signalize errors when I am trying to do that:
> "Error: inclk0 port of PLL
> interface_block_hes:INB|hes_plla:u2|altpll:altpll_component|pll must be
> driven by a non-inverted input pin or, in a fast PLL, the output of a
PLL".
>
> Regards,
> Krzysiek
>
>
>
>

Hello,

I have a problem with Stratix's PLLs.
I want to feed input of Enhanced PLL from Fast PLL and Enhanced PLL form
Enhanced PLL.

CLK input -> Fast PLL     -> Enhanced PLL -> PLL output
                                         -> other logic
 or
CLK input -> Enhanced PLL    -> Enhanced PLL -> PLL output
                                                 -> other logic

Is this two configuration possible to achieve in EP1S25 device?

Quartus 3 signalize errors when I am trying to do that:
"Error: inclk0 port of PLL
interface_block_hes:INB|hes_plla:u2|altpll:altpll_component|pll must be
driven by a non-inverted input pin or, in a fast PLL, the output of a PLL".

Regards,
Krzysiek