Hello Mark,
Yes you are right, the UART_RDY depends on the state of the
transmission. What I meant to say was that when the transmission of the
data ends, TX goes high and UART_RDY is asserted. This is a design I
found on the web. It is originally from Quicklogic, but I modified it
so that it transmits 8 bit data and then another 8 bit data before the
state machine asserts the UART_RDY.
Below is the part of the code:
BEGIN
--// Paritycycle = 1 on next to last cycle, this means when tsr[1] gets
tag2.
paritycycle <= tsr(1) AND NOT (tag2 OR tag1 OR tsr(7) OR tsr(6) OR
tsr(5) OR tsr(4) OR tsr(3) OR tsr(2));
--// txdone = 1 when done shifting, this means when tx gets tag2.
txdone <= NOT (tag2 OR tag1 OR tsr(7) OR tsr(6) OR tsr(5) OR tsr(4) OR
tsr(3) OR tsr(2) OR tsr(1) OR tsr(0));
data_latch: PROCESS(write, data)
BEGIN
IF ( write = '0' ) THEN
data1 <= data(15 downto 8);
data2 <= data(7 downto 0);
END IF;
END PROCESS;
thr_write : PROCESS ( write, txdone)
variable count1 : std_logic;
BEGIN
IF (write'event AND write = '1' ) THEN
thr <= data1;
count1 := '1';
ELSIF (txdone'event AND ( txdone='1'))AND count1 = '1' THEN
thr <= data2;
count <= '1';
count1:= '0' ;
ElSE count <='0';
END IF;
END PROCESS;
shift_out : PROCESS (txclk, reset)
BEGIN
IF (reset = '1') THEN
tsr <= (OTHERS => '0');
tag2 <= '0';
tag1 <= '0';
txparity <= paritymode;
tx <= '1';
txrdy <= '0';
ELSIF txclk = '1' AND txclk'EVENT THEN
IF (txdone='1' AND txdatardy = '1' ) OR ( txdone ='1' AND
count = '1' )THEN
-- load_data1;
tsr <= thr;
tag2 <= '1';
tag1 <= '1';
txparity <= paritymode;
tx <= '0';
ELSE
-- shift_data;
tsr <= '0'&tsr(7 downto 1);
tsr(7) <= tag1;
tag1 <= tag2;
tag2 <= '0';
txparity <= txparity XOR tsr(0);
IF (txdone = '1') THEN
tx <= '1';
IF (txdone = '1' AND count = '0') THEN
txrdy <= '1';
end if;
ELSIF (paritycycle = '1') THEN
tx <= txparity;
txrdy <= '0';
ELSE
tx <= tsr(0);
txrdy <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (mclkx16, reset)
BEGIN
IF (reset='1') THEN
txdatardy <= '0';
write2 <= '1';
write1 <= '1';
txdone1 <= '1';
ELSIF mclkx16 = '1' AND mclkx16'EVENT THEN
IF (write1 = '1' AND write2 = '0') THEN
txdatardy <= '1';
ELSIF (txdone = '0' AND txdone1 = '1') THEN
txdatardy <= '0';
END IF;
write2 <= write1;
write1 <= write;
txdone1 <= txdone;
END IF;
END PROCESS;
Reply by Mark McDougall●May 11, 20062006-05-11
sandeepbabel@gmail.com wrote:
> In the simulation, the transmission line of the UART is at HIGH when
> NOT transmitting anything, when I provide it with some data value and
> a write signal, It transmits it and then goes back high again. When
> the transmission is completed another signal called UART_RDY is
> asserted and that indicates that I can load in the next data value.
>
> In the actual synthesised design, the TX line keeps transmitting some
> random pattern over and over again, and is not held at HIGH state
> when I power the chip on. In other words the UART_RDY signal is never
> asserted, which implies that I cannot load data values from the PCI
> bus, as it is always waiting for the UART_RDY signal to be asserted.
I can't imagine the TX line state has anything to do with the UART_RDY
signal - there shouldn't be any feedback required here. UART_RDY I
would've thought depends only on the state machine of the transmitter,
and when the last bit is clocked out of the transmit register, then
UART_RDY is asserted.
The fact that TX line isn't held high is a problem - and given the
behaviour I'd suspect clocking problems? Have you checked the clock to
the UART with the logic analyzer functionality of your synthesis tools?
BTW what's the UART core doing when there's nothing to xmit? Is it
holding TX high itself, or tri-stating and assuming you have a pullup?
Is this your UART design BTW?
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Reply by ●May 11, 20062006-05-11
Hello Mark,
I have done many runs on the actual chip and also the smulation. Here
are the major differences that I have noticed and are a possible cause
of failure for the actual chip.
In the simulation, the transmission line of the UART is at HIGH when
NOT transmitting anything, when I provide it with some data value and a
write signal, It transmits it and then goes back high again. When the
transmission is completed another signal called UART_RDY is asserted
and that indicates that I can load in the next data value.
In the actual synthesised design, the TX line keeps transmitting some
random pattern over and over again, and is not held at HIGH state when
I power the chip on. In other words the UART_RDY signal is never
asserted, which implies that I cannot load data values from the PCI
bus, as it is always waiting for the UART_RDY signal to be asserted.
I have very little experience with ASIC/FPGA design, hence I am not
able to come up with a way to hold the TX line at HIGH when the chip
powers up. I have to stop the TX line from behaving in a random manner
so that I can read the UART_RDY signal and then load data values from
the PCI bus into it.
Please advise.
Thank you,
Sandeep
Reply by Mark McDougall●May 10, 20062006-05-10
sandeepbabel@gmail.com wrote:
> I am working on a chip design, where the frontend is interfaced to
> PCI bus and the backend has asynchronous FIFOs and a UART. I load the
> data into the FIFO at 33 MHz and then read it at 40 mhz and pass it
> to the UART module to transmit the data out. The design works great
> in simulation, but it is giving me entirely different results when i
> check it through a logic analyzer on the actual chip. I don't know
> what I am doing wrong. Please advise.
I'm not sure how anyone can help you with such a terse description of
what you're trying to do and, worse still, what results you are getting?!?
For example, if would be helpful to explain - at the very least - what
you're actually measuring, what the measurements are, and how they
differ to what you expect.
What have you tried - common-sense troubleshooting should provide
*plenty* of options before you need to post to this newsgroup?
First step is to narrow down where the problem lies. Can you implement a
register and successfully read/write over PCI? Can you provide a fixed
pattern to the data-out register on the UART and see that? Can you seed
the FIFO with fixed data and see that? And so on...
As for simulation vs synthesis, most commonly it's due to the
simulation's stimulus (inputs) being different to (or only a small,
non-representative sample of) the real-world signals. eg. in your case
PCI bus transactions, or clocking, such as the phase relationship
between your clock domains. Another possibility is that you're relying
on non-synthesisable elements of your HDL for 'correct' operation under
simulation.
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Reply by ●May 9, 20062006-05-09
Hi all,
I am working on a chip design, where the frontend is interfaced to PCI
bus and the backend has asynchronous FIFOs and a UART. I load the data
into the FIFO at 33 MHz and then read it at 40 mhz and pass it to the
UART module to transmit the data out. The design works great in
simulation, but it is giving me entirely different results when i check
it through a logic analyzer on the actual chip. I don't know what I am
doing wrong. Please advise.
Thank you
Sandeep