On Sun, 21 May 2006 01:09:20 -0700, John Adair wrote:

> Franco
> 
> If you want a European supplier have a look at our range here <http://www.enterpoint.co.uk/boardproducts.html>. For a very low cost board our Raggedstone1 RS1-400 is GBP&#4294967295; 50 approx 75 Euro plus VAT if it applies. These boards also have the capability to be built into arrays and can either operate in a PCI slot or stand alone (with adaptor) on the bench.
> 
> If your DSP function is intensive I would consider moving upmarket to a Virtex-4 based board. They have much more memory and faster and more multipliers.

John--

You really need to cut down on your line lengths.


    ~Dave~

Franco

If you want a European supplier have a look at our range here <http://www.enterpoint.co.uk/boardproducts.html>. For a very low cost board our Raggedstone1 RS1-400 is GBP&#4294967295; 50 approx 75 Euro plus VAT if it applies. These boards also have the capability to be built into arrays and can either operate in a PCI slot or stand alone (with adaptor) on the bench.

If your DSP function is intensive I would consider moving upmarket to a Virtex-4 based board. They have much more memory and faster and more multipliers.

Franco Tiratore schrieb:

> There are some RF and EM experts in our group, what we are missing is
> FPGA/digital design/VHDL expertise...
> At the beginning we will work with a randomly-generated bit stream...
> Or at least we can use a waveform generator...
> Can you suggest me... how can we generate such a clock? (Considering
> for example the Spartan3 board).

Use a crystal clock (30...100 MHz) to feed the FPGA, use a DCM to 
multiply the clock to the appropriate frequency/2, lets say 160 MHz.

Use a second DCM to phase shift this clock by 90 degree.
Wiht the normal (not phase shifted clock) generate your bit pattern and 
push is out of the FPGA using DDR flipflops.
The phase shifted clock is used to generate the clock signal for the 
datastream with centered transitions relative to the data.

Read alot of Xilinx datasheets and application notes. The provide tons 
of very valueable informations.

> And another point... Can you address me to some board vendor who can
> ship to Europe that "evaluation board"? Some link? Considering the low
> cost of the Spartan 3 evaluation board, I think I can risk to buy it
> for my personal use, at least I will use it for educational purposes
> even if it will not fit the final project... But what are the
> differences between the evaluation board and the standard one?

What do you mean by standard one? A evaluation board contains the FPGA 
and some peripherials like RAM, RS232, LED, LCD, FLASH, Ethernet 
(depending on the board) and connectors. Its read to use. Just download 
the right bitfile and you are done.

http://www.altium.com/Products/NanoBoardNB1/
http://www.aufzu.de/FPGA/boards.html

Regards
Falk

On Fri, 19 May 2006 19:07:51 +0200, Falk Brunner <Falk.Brunner@gmx.de>
wrote:

>Yes. You need a good connection with appropiate termination from your 
>signal source to the FPGA. Coax cable or impedance matched PCB trace. 
>Ribbon may work too, if used properly (as always ;-). Also clocking 
>might bite you. Whats the source? Is there a clock signal availabe to 
>the datastream?

There are some RF and EM experts in our group, what we are missing is
FPGA/digital design/VHDL expertise...
At the beginning we will work with a randomly-generated bit stream...
Or at least we can use a waveform generator...
Can you suggest me... how can we generate such a clock? (Considering
for example the Spartan3 board).

And another point... Can you address me to some board vendor who can
ship to Europe that "evaluation board"? Some link? Considering the low
cost of the Spartan 3 evaluation board, I think I can risk to buy it
for my personal use, at least I will use it for educational purposes
even if it will not fit the final project... But what are the
differences between the evaluation board and the standard one?

>Regards
>Falk

Gruesse,
Franco

Franco Tiratore schrieb:

Hello,

>>Depends on your abilities. 384 Mbit/s on a single lane could be a
>>problem if you dont know what you are doing.
> 
> 
> Do you mean... transmission lines issues?

Yes. You need a good connection with appropiate termination from your 
signal source to the FPGA. Coax cable or impedance matched PCB trace. 
Ribbon may work too, if used properly (as always ;-). Also clocking 
might bite you. Whats the source? Is there a clock signal availabe to 
the datastream?

Regards
Falk

Servus, Falk!


Falk Brunner ha scritto:
> Franco Tiratore schrieb:
> > Hi all.
> > I'm a total newbie to FPGA programming, therefore I'm looking for
> > suggestions.

> Hmm.

:o)


> > Do you think it can be easily implemented on an FPGA?
> Easy is a relative term. I you have the expirience, its rather easy. Are
> YOU sure you want to strart with such a project?

These are the main specs of the final project, which will take a lot of
time for the complete development (more than one year for sure). At the
beginning I will start with a scaled down version of the same project,
anyway since we still have to buy the board we want one that can fit
the final specs. So don't worry about my inexperience... :o)


> A Spartan-3 should do the job.
> 100 bucks for an evaluation board.

Really so cheap?
Sounds great!
I will investigate immediately!


> Depends on your abilities. 384 Mbit/s on a single lane could be a
> problem if you dont know what you are doing.

Do you mean... transmission lines issues?


> I dont know about the FFT, but 64 point in 1 us sounds quite fast.

>From previous posts, it seems that with fixed-point precision this
shouldn't be a critical point...


> Regards
> Falk

Gruesse,
Franco

Franco Tiratore schrieb:

> Hi all.
> I'm a total newbie to FPGA programming, therefore I'm looking for
> suggestions.

Hmm.

> In my project I have the following specs (these are only the critical
> ones, the whole project consists of additional blocks):
> - 384 Mbit/s input bitrate
> - 64-point FFT block, complex numbers with 16 bit fixed-point precision
> for each real number, the calculation must be performed in less than
> 1us
> - 80 Ms/s output symbol rate
> Do you think it can be easily implemented on an FPGA?

Easy is a relative term. I you have the expirience, its rather easy. Are 
YOU sure you want to strart with such a project?

> If yes, can you address me to some FPGA model? (At least, I would like

A Spartan-3 should do the job.

> to know the price range)

100 bucks for an evaluation board.

> If not, what is the critical part?

Depends on your abilities. 384 Mbit/s on a single lane could be a 
problem if you dont know what you are doing.

I dont know about the FFT, but 64 point in 1 us sounds quite fast.

Regards
Falk

Hi all.
I'm a total newbie to FPGA programming, therefore I'm looking for
suggestions.
In my project I have the following specs (these are only the critical
ones, the whole project consists of additional blocks):
- 384 Mbit/s input bitrate
- 64-point FFT block, complex numbers with 16 bit fixed-point precision
for each real number, the calculation must be performed in less than
1us
- 80 Ms/s output symbol rate
Do you think it can be easily implemented on an FPGA?
If yes, can you address me to some FPGA model? (At least, I would like
to know the price range)
If not, what is the critical part?

Ciao,
Franco Tiratore