srini,

See below,

Austin

srini wrote:
> Hi,
> I am using the VirtexII DCM in my design to generate the master clock
> for all the modules in my design. The input freq is 20.48 MHz and the
> output freq from DCM is 61.44 MHz. The "LOCKED" signal from DCM is
> AND'ed with the system reset and given as reset to all the modules in
> the design.

Make sure that you do not connect anything to CLKFB, CLK0/90/180/270/2X,
2X_b, and CLKDV (these are all DLL outputs and input, and if the DLL is
used with the DFS, 20.48 is too low a frequency and it will never lock).

> When I generate the DCM using Coregen, there is a option "wait for DCM
> lock before DONE signal goes high" when I click the "Advanced" button.

This allows the DCM to lock before allowing DONE to go high:  do not use
it.  Rather, it is safer to reset the DCM when you know the input clock
is good, and stable.

> Can anyone clarify me what will happen if I dont check this option ?

DONE goes high without checking that the DCM is locked.

> Will it affect the startup operation or the functioning of the FPGA
> after startup?

Yes.  With it checked, the DCM is locked when DONE goes high.  Without
it, the state of the DCM is under your control.

 What is the significance of this option?

If your clock input to the DCM is always stable, and the CLKFB (if used
as a DLL) does not come from an external source, this option is a
convenient way to start up the DCM, and never use the RESET to the DCM
(simplest mode).

It is fraught with difficulties in the real world, as guaranteeing the
clocks are good before DONE goes high is not possible in most circumstances.

Rather, do not wait for LOCKED before DONE, and instantiate a SRL16
clocked by CLKIN so that when the device DONE goes high, a '1' is
shifted into the SRL16 whose output drives the RESET input of the DCM
(and also goes back and sends a '0' into the SRL16).  This clever shift
register reset circuit then clocks 16 times till a 1 comes out which
resets the DCM, and then 16 clocks later, reset goes to a '0' again.  At
that point, LOCKED will go high when the DCM locks, and that should gate
all your logic to start up (go to state 0, reset or enable your logic,
etc.).

I think it is better you trust your own design, and be in control of it,
rather than use the "must lock before DONE goes high" backwards
compatible feature (this feature was originally in the original first
Virtex - which is 7 years old now).

Hi,
I am using the VirtexII DCM in my design to generate the master clock
for all the modules in my design. The input freq is 20.48 MHz and the
output freq from DCM is 61.44 MHz. The "LOCKED" signal from DCM is
AND'ed with the system reset and given as reset to all the modules in
the design.
When I generate the DCM using Coregen, there is a option "wait for DCM
lock before DONE signal goes high" when I click the "Advanced" button.
Can anyone clarify me what will happen if I dont check this option ?
Will it affect the startup operation or the functioning of the FPGA
after startup? What is the significance of this option?
When I check this option, I am getting a message that I should specify
a value for LCK_dll in the bitgen options. First of all, I am not
finding any option on that name in bitgen. I felt that the "Release
DLL" option maybe the LCK_dll option which the ISE tutorial refers to.
Plz let me know whether I am correct.
I also dont know what value I should enter for this LCK_dll option. How
to decide on the number of clock cycles? 

Thanks & Regards,
Srini.