> 33 MHz will be a lot easier to get working than 66 MHz if you're doing
> this from scratch.  I don't recall the precise constraints for 33 off
> the top of my head though.

Tsu 7 ns, Tco 11 nS, Clk 33 MHz

As you said, easy enough to meet as you can register a lot of the
signals in, it's only a few of the controls which are critical.


Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

naveenk23@yahoo.com (naveen) wrote in message news:<27641594.0311201557.6d52d8d0@posting.google.com>...
> Hi all,
>         I have a small clarification. I am using Quartus 2 Tool for
> Synthesis and Place and route of a PCI System. I want to know if we
> can set some options for set up time for PCI Clock Seperately.
> Thanks
> Naveen

You'll need to set Tsu constraints on your inputs (3 ns for 66 MHz
PCI), Tco constraints on your outputs (6 ns for 66 MHz PCI) and a
clock period (Fmax) constraint on your clock (66.66 MHz I think for 66
MHz PCI).

At least that's the high-level view of the constraints.  I believe it
is possible to relax the Tsu and Tco constraints on some paths by
inserting wait states, but I'm not an expert on PCI cores.

You can set pretty much as complicated a set of constraints as you'd
like in Quartus.  Setting a Tsu constraint on an IO will constrain all
paths from that IO to all reachable registers.  Setting a
"point-to-point" Tsu constraint on a source IO and a destination
register constraints only the paths between the two.

33 MHz will be a lot easier to get working than 66 MHz if you're doing
this from scratch.  I don't recall the precise constraints for 33 off
the top of my head though.

Vaughn
Altera

Hi all,
        I have a small clarification. I am using Quartus 2 Tool for
Synthesis and Place and route of a PCI System. I want to know if we
can set some options for set up time for PCI Clock Seperately.
Thanks
Naveen