Many thanks, Austin, for your reply.
---
Jim

"Austin Lesea" <austin@xilinx.com> wrote in message 
news:e5ki8v$8a712@xco-news.xilinx.com...
> Jim,
>
> The CPLD you note is a 3.3V part, with a 5V input tolerance.  Any
> outputs will swing from 0 to 3.3V, not 0 to 5V.
>
> Other than that, inverting, or not inverting a signal is no problem
> (selection of a 2:1 mux with the inverted and non-inverted signal as
> inputs, output driving a pin).
>
> The jitter added is on the order of 20-50 ps p-p (a simple 74HC04
> inverter adds as much, and the delay will be something that you can get
> as a report from the design tools).
>
> Austin
>
> Jim wrote:
>> Hi,
>>
>> Apologies upfront if this is a really basic question, as I am rather new 
>> to
>> CPLDs.
>>
>> We have a 0-5V squarewave (approx 1MHz, approx 50% duty) that we wish to 
>> use
>> as the clock to a Xilinx CPLD (XC9572XL). We need to select at runtime
>> whether to clock on its rising edge or its falling edge. To achieve this, 
>> my
>> current thinking is to run this signal into a spare pin on the Xilinx. A
>> control line into the Xilinx will tell it to either invert the signal or
>> output it unchanged. This inverted/uninverted clock signal will then 
>> connect
>> to the Xilinx pin assigned as its clock source.
>>
>> Just wondering, does that sound seinsble, and is there anything I should 
>> be
>> wary of doing it this way? As I say, I am new to CPLDs so please don't 
>> rule
>> out something you believe to be too obvious to mention, thanks! The only
>> thing I can think of currently is the amount of delay added by the extra
>> routing of the clock, plus increased jitter. However, they should both be
>> within our requirements.
>>
>> Many thanks in advance.
>>
>> ---
>> Jim
>>
>>
>> 

Jim,

The CPLD you note is a 3.3V part, with a 5V input tolerance.  Any
outputs will swing from 0 to 3.3V, not 0 to 5V.

Other than that, inverting, or not inverting a signal is no problem
(selection of a 2:1 mux with the inverted and non-inverted signal as
inputs, output driving a pin).

The jitter added is on the order of 20-50 ps p-p (a simple 74HC04
inverter adds as much, and the delay will be something that you can get
as a report from the design tools).

Austin

Jim wrote:
> Hi,
> 
> Apologies upfront if this is a really basic question, as I am rather new to 
> CPLDs.
> 
> We have a 0-5V squarewave (approx 1MHz, approx 50% duty) that we wish to use 
> as the clock to a Xilinx CPLD (XC9572XL). We need to select at runtime 
> whether to clock on its rising edge or its falling edge. To achieve this, my 
> current thinking is to run this signal into a spare pin on the Xilinx. A 
> control line into the Xilinx will tell it to either invert the signal or 
> output it unchanged. This inverted/uninverted clock signal will then connect 
> to the Xilinx pin assigned as its clock source.
> 
> Just wondering, does that sound seinsble, and is there anything I should be 
> wary of doing it this way? As I say, I am new to CPLDs so please don't rule 
> out something you believe to be too obvious to mention, thanks! The only 
> thing I can think of currently is the amount of delay added by the extra 
> routing of the clock, plus increased jitter. However, they should both be 
> within our requirements.
> 
> Many thanks in advance.
> 
> ---
> Jim
> 
> 
> 

Hi,

Apologies upfront if this is a really basic question, as I am rather new to 
CPLDs.

We have a 0-5V squarewave (approx 1MHz, approx 50% duty) that we wish to use 
as the clock to a Xilinx CPLD (XC9572XL). We need to select at runtime 
whether to clock on its rising edge or its falling edge. To achieve this, my 
current thinking is to run this signal into a spare pin on the Xilinx. A 
control line into the Xilinx will tell it to either invert the signal or 
output it unchanged. This inverted/uninverted clock signal will then connect 
to the Xilinx pin assigned as its clock source.

Just wondering, does that sound seinsble, and is there anything I should be 
wary of doing it this way? As I say, I am new to CPLDs so please don't rule 
out something you believe to be too obvious to mention, thanks! The only 
thing I can think of currently is the amount of delay added by the extra 
routing of the clock, plus increased jitter. However, they should both be 
within our requirements.

Many thanks in advance.

---
Jim