> Hi,
> you made a common mistake. Multiple assignment.
> In both processes writeramb and Algorithm you assign values to signalramb.
>
> Your simulator detects this and resolves the conflicting values to 'X'.
> Your synthesis tool will generate an error.
>
> Think of processes as integrated circuits. (Their enclosure is Begin and
> end) There you would never tie normal (compared to tristate) outputs
> together because it may lead to shortening the supply and destruction of
> the ICs.
>
> Furthermore, If you want to enable some clocked process better write:
>
> if rising_edge(clk) then
> if trigger = '1' then
> --do something
> end if;
> end if;
>
> If you want to intialize your ram, you have to do it in another way.
> For example in a single process.
>
> have a nice synthesis
> Eilert
>
> ZHI schrieb:
> >
> > ******************************Algorithm*************************************
> > Algorithm: process (trigger, clk)
> > ............................................................
> > begin
> > if trigger ='1' then
> > if clk'event and clk='1' then
> ....
> > end if;
> > end if;
> >
> > ***************************************************************************************
> > Though I put three process here,I want the algorithm process to be
> > executed after all the data sent into the RAMs. I put 'Trigger' as one
> > of sensitivity parameters in process Algorithm.
> > RAMr works normally but the RAMb always have conflict problem (For
> > example ,the data 0000000000000001 saved RAMB become 000000000000000X).
> >
> > When I removed the codes(ramb(0)<=.....) whick is concerned with RAMb
> > in the process of Algorithm. Then there is not conflict problem anymore
> > in RAMb.
> >
> > My question is why Algorithm process effects the WriteRAMb process.
> > Because I set 'Trigger=1' when the all data were sent into RAMs.Then
> > the process Algorithm is activated.
Reply by backhus●June 16, 20062006-06-16
Hi,
you made a common mistake. Multiple assignment.
In both processes writeramb and Algorithm you assign values to signalramb.
Your simulator detects this and resolves the conflicting values to 'X'.
Your synthesis tool will generate an error.
Think of processes as integrated circuits. (Their enclosure is Begin and
end) There you would never tie normal (compared to tristate) outputs
together because it may lead to shortening the supply and destruction of
the ICs.
Furthermore, If you want to enable some clocked process better write:
if rising_edge(clk) then
if trigger = '1' then
--do something
end if;
end if;
If you want to intialize your ram, you have to do it in another way.
For example in a single process.
have a nice synthesis
Eilert
ZHI schrieb:
>
> ******************************Algorithm*************************************
> Algorithm: process (trigger, clk)
> ............................................................
> begin
> if trigger ='1' then
> if clk'event and clk='1' then
....
> end if;
> end if;
>
> ***************************************************************************************
> Though I put three process here,I want the algorithm process to be
> executed after all the data sent into the RAMs. I put 'Trigger' as one
> of sensitivity parameters in process Algorithm.
> RAMr works normally but the RAMb always have conflict problem (For
> example ,the data 0000000000000001 saved RAMB become 000000000000000X).
>
> When I removed the codes(ramb(0)<=.....) whick is concerned with RAMb
> in the process of Algorithm. Then there is not conflict problem anymore
> in RAMb.
>
> My question is why Algorithm process effects the WriteRAMb process.
> Because I set 'Trigger=1' when the all data were sent into RAMs.Then
> the process Algorithm is activated.
Reply by ZHI●June 15, 20062006-06-15
Hello, I a newer to vhdl. I am trying to change my algorithm form
matlab to vhdl. I met RAMs conflict when I did it.
***********************************************************
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity dcdtest3 is
generic (Nit: integer:=20000; H: integer :=1; Mb: integer :=6);
port
( clk: in std_logic;
en: in std_logic;
b: in std_logic_vector(15 downto 0);
r: in std_logic_vector(15 downto 0);
dout1: out std_logic_vector(15 downto 0);
dout2: out std_logic_vector(15 downto 0));
end dcdtest3;
architecture behaviour of dcdtest3 is
function maxfunction( arg1, arg2, arg3: std_logic_vector (15 downto
0)) return std_logic_vector ;
type ram_type1 is array (0 to 3) of std_logic_vector(15 downto 0);
signal ramb : ram_type1 :=(others =>(others=>'0'));
signal ramh : ram_type1 :=(others =>(others=>'0'));
signal ramrtmp: ram_type1 :=(others =>(others=>'0'));
type ram_type2 is array (0 to 15) of std_logic_vector (15 downto 0);
signal ramr : ram_type2:=(others =>(others=>'0'));
signal douts1: std_logic_vector(15 downto 0) :=(others=>'0');
signal douts2: std_logic_vector(15 downto 0) :=(others=>'0');
signal trigger: std_logic :='0';
begin
dout1<=douts1;
dout2<=douts2;
*************************write data into
RAMB******************************
writeramb: process(clk)
variable indexb: integer range 0 to 4 :=0;
variable web: std_logic :='1';
variable reb : std_logic :='0';
begin
if clk'event and clk='1' then
if web='1' then
ramb(indexb)<=b;
indexb:=indexb+1;
if indexb=4 then
indexb :=0;
web :='0';
end if;
end if;
end if;
end process;
*********************write data into
RAMR******************************************
writeramr: process(clk)
variable indexr: integer range 0 to 16 :=0; .
variable wer: std_logic :='1';
begin
if clk'event and clk='1' then
if wer='1' then
ramr(indexr)<=r;
end if;
if indexr=0 then
ramrtmp(0) <= ramr(indexr);
elsif indexr=5 then
ramrtmp(1) <=ramr(indexr);
elsif indexr=10 then
ramrtmp(2) <=ramr(indexr);
elsif indexr=15 then
trigger <='1'; ***********************
ramrtmp(3) <=ramr(indexr);
end if;
indexr :=indexr+1;
if indexr =16 then
indexr :=0;
wer :='0';
end if;
end if;
end process;
******************************Algorithm*************************************
Algorithm: process (trigger, clk)
............................................................
begin
if trigger ='1' then
if clk'event and clk='1' then
............................................................
........................................................
-- ramb(0) <=ramb(index)+ conv_std_logic_vector(ramrtemp,16);
-- ramb(1) <=ramb(index)+ conv_std_logic_vector(ramrtemp1,16);
-- ramb(2) <=ramb(index)+ conv_std_logic_vector(ramrtemp2,16);
-- ramb(3) <=ramb(index)+ conv_std_logic_vector(ramrtemp3,16);
...........................................................................
end if;
end if;
***************************************************************************************
Though I put three process here,I want the algorithm process to be
executed after all the data sent into the RAMs. I put 'Trigger' as one
of sensitivity parameters in process Algorithm.
RAMr works normally but the RAMb always have conflict problem (For
example ,the data 0000000000000001 saved RAMB become 000000000000000X).
When I removed the codes(ramb(0)<=.....) whick is concerned with RAMb
in the process of Algorithm. Then there is not conflict problem anymore
in RAMb.
My question is why Algorithm process effects the WriteRAMb process.
Because I set 'Trigger=1' when the all data were sent into RAMs.Then
the process Algorithm is activated.
Hopefully you can understand the problem what i described here and give
some suggestions. Thanks
Zhi