Thank you for your help, I did manage to make my VHDL bench compile with the 
verilog model.

St�phane.

"Duane Clark" <junkmail@junkmail.com> a &#4294967295;crit dans le message de news: 
SYTng.73160$4L1.13281@newssvr11.news.prodigy.com...
> sjulhes wrote:
>> Thanks for the answers but as I don't know anything in verilog (!) could 
>> someone give me a little example of how to declare a verilog component in 
>> a vhdl file and how to instanciate it in the vhdl file.
>
> There is no special syntax for Verilog models. For instance, I use the 
> Micron models for the mt16vddf12864. It starts out with:
>
> module mt16vddf12864 (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, 
> Cas_n, We_n, Dm);
>   inout [0 : 63] Dq;
>   inout  [0 : 7] Dqs;
>   input [0 : 12] Addr;
>   input  [0 : 1] Ba;
>   input  [0 : 2] Clk;
>   input  [0 : 2] Clk_n;
>   input  [0 : 1] Cke;
>   input  [0 : 1] Cs_n;
>   input          Ras_n;
>   input          Cas_n;
>   input          We_n;
>   input  [0 : 7] Dm;
>
>
> And it is compiled into the work directory with:
> vlog mt16vddf12864.v
>
>
> My testbench contains:
>
>    -- MICRON DDR SDRAM Simulation Model
>    DIMM : entity mem.MT16VDDF12864
>    port map (
>       Dq             => DDR_DQ,
>       Dqs            => DDR_DQS,
> --      Addr           => DDR_Addr(C_DDR_AWIDTH-11 to 12),
>       Addr           => DDR_Addr(0 to 12),
>       Ba             => DDR_BankAddr,
>       Clk(0)         => DDR_Clk_0,
>       Clk(1)         => DDR_Clk_1,
>       Clk(2)         => DDR_Clk_0,
>       Clk_n(0)       => DDR_Clkn_0,
>       Clk_n(1)       => DDR_Clkn_1,
>       Clk_n(2)       => DDR_Clkn_0,
>       Cke            => DDR_CKE,
>       Cs_n           => DDR_CSn,
>       Ras_n          => DDR_RASn,
>       Cas_n          => DDR_CASn,
>       We_n           => DDR_WEn,
>       Dm             => DDR_DM
>    );
>
> Where my project.mpf file contains:
> [Library]
> mem = $MODELS/mem/work
>
> Which is where I compiled the Micron models. 

"sjulhes" <t@aol.fr> wrote in message news:449fff97$0$31655$636a55ce@news.free.fr...
> Thanks for the answers but as I don't know anything in verilog (!) could someone give me a little 
> example of how to declare a verilog component in a vhdl file and how to instanciate it in the vhdl 
> file.
> Thank you.
> St&#4294967295;phane.


As Duane shows below(/above), a single wire maps to std_logic and a vector to a
std_logic_vector of the correct width.


Nial. 

sjulhes wrote:
> Thanks for the answers but as I don't know anything in verilog (!) could 
> someone give me a little example of how to declare a verilog component in a 
> vhdl file and how to instanciate it in the vhdl file.

There is no special syntax for Verilog models. For instance, I use the 
Micron models for the mt16vddf12864. It starts out with:

module mt16vddf12864 (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, 
Cas_n, We_n, Dm);
   inout [0 : 63] Dq;
   inout  [0 : 7] Dqs;
   input [0 : 12] Addr;
   input  [0 : 1] Ba;
   input  [0 : 2] Clk;
   input  [0 : 2] Clk_n;
   input  [0 : 1] Cke;
   input  [0 : 1] Cs_n;
   input          Ras_n;
   input          Cas_n;
   input          We_n;
   input  [0 : 7] Dm;


And it is compiled into the work directory with:
vlog mt16vddf12864.v


My testbench contains:

    -- MICRON DDR SDRAM Simulation Model
    DIMM : entity mem.MT16VDDF12864
    port map (
       Dq             => DDR_DQ,
       Dqs            => DDR_DQS,
--      Addr           => DDR_Addr(C_DDR_AWIDTH-11 to 12),
       Addr           => DDR_Addr(0 to 12),
       Ba             => DDR_BankAddr,
       Clk(0)         => DDR_Clk_0,
       Clk(1)         => DDR_Clk_1,
       Clk(2)         => DDR_Clk_0,
       Clk_n(0)       => DDR_Clkn_0,
       Clk_n(1)       => DDR_Clkn_1,
       Clk_n(2)       => DDR_Clkn_0,
       Cke            => DDR_CKE,
       Cs_n           => DDR_CSn,
       Ras_n          => DDR_RASn,
       Cas_n          => DDR_CASn,
       We_n           => DDR_WEn,
       Dm             => DDR_DM
    );

Where my project.mpf file contains:
[Library]
mem = $MODELS/mem/work

Which is where I compiled the Micron models.

Thanks for the answers but as I don't know anything in verilog (!) could 
someone give me a little example of how to declare a verilog component in a 
vhdl file and how to instanciate it in the vhdl file.

Thank you.

St�phane.

"Sean Durkin" <smd@despammed.com> a &#4294967295;crit dans le message de news: 
449fecbb$1@news.fhg.de...
> sjulhes wrote:
>> Hello all,
>>
>> I'm desigining a Xilinx FPGA with a sdram controller for a 
>> MT48LC8M16A2-75
>> memory but I can not find anymore the VHDL model on the Micron's website 
>> !
>>
>> Does someone know if it still possible to get a VHDL from Micron ?
> I contacted them to get VHDL models just last week and got the following
> reply:
>
> "Unfortunately we no longer support VHDL models, as they have not been
> actively developed in many years.
> If you absolutely require a VHDL model, I suggest using a 3rd party
> model that can be compiled into VHDL (or many other languages).
> www.denali.com or www.synopsys.com"
>
> So unless you can find an older model somewhere (they used to have VHDL
> models), there's no VHDL from Micron anymore.
>
>> As there still verilog models on the Micron's website and as my modelsim
>> simulator can handle both vhdl and verilog, can someone give some clues 
>> to
>> use this verilog sdram model in my vhdl simulation project ?
> It's pretty much the same as you would do it with VHDL. Just add it to
> your project, instantiate it in your VHDL (in your testbench or
> whatever), and there you go. You just have to be able to "read" Verilog
> good enough that you can get the port descriptions for the entity. Plus,
> when you compile the Verilog model you have to specify the speed grade
> as a define, which you can normally pass to the compiler as a command
> line argument.
>
> cu,
> Sean 

sjulhes wrote:
> Hello all,
> 
> I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 
> memory but I can not find anymore the VHDL model on the Micron's website !
> 
> Does someone know if it still possible to get a VHDL from Micron ?
I contacted them to get VHDL models just last week and got the following
reply:

"Unfortunately we no longer support VHDL models, as they have not been
actively developed in many years.
If you absolutely require a VHDL model, I suggest using a 3rd party
model that can be compiled into VHDL (or many other languages).
www.denali.com or www.synopsys.com"

So unless you can find an older model somewhere (they used to have VHDL
models), there's no VHDL from Micron anymore.

> As there still verilog models on the Micron's website and as my modelsim 
> simulator can handle both vhdl and verilog, can someone give some clues to 
> use this verilog sdram model in my vhdl simulation project ?
It's pretty much the same as you would do it with VHDL. Just add it to
your project, instantiate it in your VHDL (in your testbench or
whatever), and there you go. You just have to be able to "read" Verilog
good enough that you can get the port descriptions for the entity. Plus,
when you compile the Verilog model you have to specify the speed grade
as a define, which you can normally pass to the compiler as a command
line argument.

cu,
Sean

sjulhes <t@aol.fr> wrote:
>Hello all,

>I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 
>memory but I can not find anymore the VHDL model on the Micron's website !

>Does someone know if it still possible to get a VHDL from Micron ?

>As there still verilog models on the Micron's website and as my modelsim 
>simulator can handle both vhdl and verilog, can someone give some clues to 
>use this verilog sdram model in my vhdl simulation project ?

Maybe this will work?
  www.ee.byu.edu/class/ee424/labs/MicronSDRAM/mt48lc32m8a2.vhd

Hello all,

I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 
memory but I can not find anymore the VHDL model on the Micron's website !

Does someone know if it still possible to get a VHDL from Micron ?

As there still verilog models on the Micron's website and as my modelsim 
simulator can handle both vhdl and verilog, can someone give some clues to 
use this verilog sdram model in my vhdl simulation project ?

Thank you.

St�phane.