Reply by ●July 4, 20062006-07-04
hi, Vivek
I had the same issue on the UART core.  Can you point me the link and
solution to download it?

Thanks

Frank
Vivek Menon wrote:

> Matter resolved.
> Ken pointed me to the latest UART core being shipped with the Picoblaze
> module for Virtex-II Pro designs. I had some trouble downloading the
> picoblaze module, but thanks to Ed, the UART core is working
> successfully on my board.
> Thanks once again,
> Vivek
>
>
> Ray Andraka wrote:
> > Aurelian Lazarut wrote:
> >
> > > run map with -ir (ignore RLOCs)
> > > or if you use ISE, change map propreties by unchecking "use RLOC...."
> > > Aurash
> > >
> >
> > I don't believe that will work.  I think the RLOCs are still parsed with
> > that switch set, in which case it will error out with the same complaint.
Reply by Vivek Menon ●June 29, 20062006-06-29
Matter resolved.
Ken pointed me to the latest UART core being shipped with the Picoblaze
module for Virtex-II Pro designs. I had some trouble downloading the
picoblaze module, but thanks to Ed, the UART core is working
successfully on my board.
Thanks once again,
Vivek


Ray Andraka wrote:

> Aurelian Lazarut wrote:
>
> > run map with -ir (ignore RLOCs)
> > or if you use ISE, change map propreties by unchecking "use RLOC...."
> > Aurash
> >
>
> I don't believe that will work.  I think the RLOCs are still parsed with
> that switch set, in which case it will error out with the same complaint.
Reply by Ray Andraka ●June 29, 20062006-06-29
Aurelian Lazarut wrote:


> run map with -ir (ignore RLOCs)
> or if you use ISE, change map propreties by unchecking "use RLOC...."
> Aurash
> 


I don't believe that will work.  I think the RLOCs are still parsed with 
that switch set, in which case it will error out with the same complaint.
Reply by Ray Andraka ●June 29, 20062006-06-29
Vivek Menon wrote:


> I came across the Xilinx application xapp223 for the implementation of
> the UART cores. I have been trying various implementations of UART
> transmitter cores and I am trying to implement this macro on a Xilinx
> Virtex-II Pro 7 FPGA FF672 board. Now, I am using a 100 MHz clock,
> which gets divided by 162 to provide the exact clock for a baud rate of
> 38,400. I have also declared the uart_tx as a black box as per the
> README file. However, the design has a lot of errors during the mapping
> stage and I am not able to figure out the errors as I am not able to
> open the .EDN file. The sample errors I faced are:
> 
> ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on FDRE symbol
> "U1/$I1"
>    (output signal=U1/A<3>).
> ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on XORCY symbol
> "U1/$I10"
>    (output signal=U1/SUM_A2).
> ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
> "U1/$I105"
>    (output signal=U1/$Net00113_).
> ERROR:Map:6 - Bad format for RLOC constraint " R6C0.S0" on FD symbol
> "U1/$I106"
>    (output signal=U1/TX_RUN).
> ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on FD symbol
> "U1/$I107"
>    (output signal=U1/TX_START).
> ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
> "U1/$I108"
>    (output signal=U1/$Net00151_).
> ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on MUXCY symbol
> "U1/$I11"
>    (output signal=U1/CY_A2).
> 
> My ucf file for the top module is very simple:
> NET clk                LOC= D13;
> NET tx_rs232         LOC=AC6;
> NET wrn                LOC=E7;
> NET bfull            LOC=D6;
> 
> My top file declaration:
> entity rs232_test_top is
> port(
>         clk        : in std_logic;
>         wrn        : in std_logic;
>         bfull        : out std_logic;
>         tx_rs232 : out std_logic);
> end rs232_test_top;
> 
> I am guessing that the component  uart_tx is not being
> compiled/synthesized by Xilinx ISE. Please let me know if there are any
> solutions.
> Thank you,
> Vivek
> 


The problem is actually a lot simpler than that.  The design macro is 
apparently for Virtex1 or spartanII devices; the RLOC placement 
constraints are not the right style for the Virtex2 devices.

If you have access to the source code, you need to either remove the 
RLOCs altogether and hope that it meets timing without them (it probably 
  will), or change the RLOCs to the RLOC=XnYm style used in the Virtex2 
and later devices (different layout grid).  You can read about the RLOCs 
in the libraries guide, which is linked to from the XST/ISE project manager.
Reply by Vivek Menon ●June 29, 20062006-06-29
No that does not solve the problem. However, Ken asked me to use the
macros provided with picoblaze and now the ifulcrum/xapps questionnaire
which keeps crashing.
Hence I am not able to download the UART core which comes with the
Picoblaze bundle.
Thanks,
Vivek


Aurelian Lazarut wrote:

> run map with -ir (ignore RLOCs)
> or if you use ISE, change map propreties by unchecking "use RLOC...."
> Aurash
>
> Vivek Menon wrote:
>
> >I came across the Xilinx application xapp223 for the implementation of
> >the UART cores. I have been trying various implementations of UART
> >transmitter cores and I am trying to implement this macro on a Xilinx
> >Virtex-II Pro 7 FPGA FF672 board. Now, I am using a 100 MHz clock,
> >which gets divided by 162 to provide the exact clock for a baud rate of
> >38,400. I have also declared the uart_tx as a black box as per the
> >README file. However, the design has a lot of errors during the mapping
> >stage and I am not able to figure out the errors as I am not able to
> >open the .EDN file. The sample errors I faced are:
> >
> >ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on FDRE symbol
> >"U1/$I1"
> >   (output signal=U1/A<3>).
> >ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on XORCY symbol
> >"U1/$I10"
> >   (output signal=U1/SUM_A2).
> >ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
> >"U1/$I105"
> >   (output signal=U1/$Net00113_).
> >ERROR:Map:6 - Bad format for RLOC constraint " R6C0.S0" on FD symbol
> >"U1/$I106"
> >   (output signal=U1/TX_RUN).
> >ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on FD symbol
> >"U1/$I107"
> >   (output signal=U1/TX_START).
> >ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
> >"U1/$I108"
> >   (output signal=U1/$Net00151_).
> >ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on MUXCY symbol
> >"U1/$I11"
> >   (output signal=U1/CY_A2).
> >
> >My ucf file for the top module is very simple:
> >NET clk                LOC= D13;
> >NET tx_rs232         LOC=AC6;
> >NET wrn                LOC=E7;
> >NET bfull            LOC=D6;
> >
> >My top file declaration:
> >entity rs232_test_top is
> >port(
> >        clk        : in std_logic;
> >        wrn        : in std_logic;
> >        bfull        : out std_logic;
> >        tx_rs232 : out std_logic);
> >end rs232_test_top;
> >
> >I am guessing that the component  uart_tx is not being
> >compiled/synthesized by Xilinx ISE. Please let me know if there are any
> >solutions.
> >Thank you,
> >Vivek
> >
> >
> >
>
>
> --
>  __
> / /\/\ Aurelian Lazarut
> \ \  / System Verification Engineer
> / /  \ Xilinx Ireland
> \_\/\/
>  
> phone:	353 01 4032639
> fax:	353 01 4640324
Reply by Aurelian Lazarut ●June 29, 20062006-06-29
run map with -ir (ignore RLOCs)
or if you use ISE, change map propreties by unchecking "use RLOC...."
Aurash
 
Vivek Menon wrote:


>I came across the Xilinx application xapp223 for the implementation of
>the UART cores. I have been trying various implementations of UART
>transmitter cores and I am trying to implement this macro on a Xilinx
>Virtex-II Pro 7 FPGA FF672 board. Now, I am using a 100 MHz clock,
>which gets divided by 162 to provide the exact clock for a baud rate of
>38,400. I have also declared the uart_tx as a black box as per the
>README file. However, the design has a lot of errors during the mapping
>stage and I am not able to figure out the errors as I am not able to
>open the .EDN file. The sample errors I faced are:
>
>ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on FDRE symbol
>"U1/$I1"
>   (output signal=U1/A<3>).
>ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on XORCY symbol
>"U1/$I10"
>   (output signal=U1/SUM_A2).
>ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
>"U1/$I105"
>   (output signal=U1/$Net00113_).
>ERROR:Map:6 - Bad format for RLOC constraint " R6C0.S0" on FD symbol
>"U1/$I106"
>   (output signal=U1/TX_RUN).
>ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on FD symbol
>"U1/$I107"
>   (output signal=U1/TX_START).
>ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
>"U1/$I108"
>   (output signal=U1/$Net00151_).
>ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on MUXCY symbol
>"U1/$I11"
>   (output signal=U1/CY_A2).
>
>My ucf file for the top module is very simple:
>NET clk                LOC= D13;
>NET tx_rs232         LOC=AC6;
>NET wrn                LOC=E7;
>NET bfull            LOC=D6;
>
>My top file declaration:
>entity rs232_test_top is
>port(
>        clk        : in std_logic;
>        wrn        : in std_logic;
>        bfull        : out std_logic;
>        tx_rs232 : out std_logic);
>end rs232_test_top;
>
>I am guessing that the component  uart_tx is not being
>compiled/synthesized by Xilinx ISE. Please let me know if there are any
>solutions.
>Thank you,
>Vivek
>
>  
>



-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
Reply by Vivek Menon ●June 29, 20062006-06-29
I came across the Xilinx application xapp223 for the implementation of
the UART cores. I have been trying various implementations of UART
transmitter cores and I am trying to implement this macro on a Xilinx
Virtex-II Pro 7 FPGA FF672 board. Now, I am using a 100 MHz clock,
which gets divided by 162 to provide the exact clock for a baud rate of
38,400. I have also declared the uart_tx as a black box as per the
README file. However, the design has a lot of errors during the mapping
stage and I am not able to figure out the errors as I am not able to
open the .EDN file. The sample errors I faced are:

ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on FDRE symbol
"U1/$I1"
   (output signal=U1/A<3>).
ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on XORCY symbol
"U1/$I10"
   (output signal=U1/SUM_A2).
ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
"U1/$I105"
   (output signal=U1/$Net00113_).
ERROR:Map:6 - Bad format for RLOC constraint " R6C0.S0" on FD symbol
"U1/$I106"
   (output signal=U1/TX_RUN).
ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on FD symbol
"U1/$I107"
   (output signal=U1/TX_START).
ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
"U1/$I108"
   (output signal=U1/$Net00151_).
ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on MUXCY symbol
"U1/$I11"
   (output signal=U1/CY_A2).

My ucf file for the top module is very simple:
NET clk                LOC= D13;
NET tx_rs232         LOC=AC6;
NET wrn                LOC=E7;
NET bfull            LOC=D6;

My top file declaration:
entity rs232_test_top is
port(
        clk        : in std_logic;
        wrn        : in std_logic;
        bfull        : out std_logic;
        tx_rs232 : out std_logic);
end rs232_test_top;

I am guessing that the component  uart_tx is not being
compiled/synthesized by Xilinx ISE. Please let me know if there are any
solutions.
Thank you,
Vivek