> The reason for doing this is so that i can do a functional simulation
> of my design prior to synthesising it - synthesis currently takes 4
> hours ! !

Ouch, that's quite a long time for synthesis...unless by synthesis you mean
a design that's routed and ready to be downloaded into a FPGA.

If by synthesis you mean the process of just mapping VHDL into FPGA
primitives, before the place and routing is done, then perhaps instead of
synthesizing the entire design as a whole, you could synthesize it in parts.
I'm not sure how much improvement it would give you in your situation, but
we find it helpful to do when Synplify is taking a long time to synthesize.
Perhaps it's a memmory usage thing.

Well that didn't answer your original question, but the 4 hours to
synthesize stuck out at me.


Regards,
Vinh

JohhnyNorthener wrote:
> P L E A S E  somebody help.  I have a design of mixed .gdf and .vhd
> files that
> were created in MaxPlusII, which I have imported it into Quartus II
> v3.0 SP2.
> 
> What I am trying to do is to convert the complete design into VHDL
> ONLY
> 
> The reason for doing this is so that i can do a functional simulation
> of my design prior to synthesising it - synthesis currently takes 4
> hours ! !

Sounds like a good reason to write some code.
The fixed-pc license includes modelsim, which
should handle this job for you.

>     - currently, the way i am creating a VHDL ONLY representation of
> my design
>     (without synth'ing) is by 'create HDL design file for current
> file' on      every block diagram i have.

Consider using the block diagrams only
as a guide to write your own vhdl synth code.
Do a bit at a time using a modelsim compile
to check syntax.

Write a simple testbench before attempting synthesis.

If rewriting the synth code is too much trouble,
consider writing a modelsim testbench only for
your existing .vho netlist.


  -- Mike Treseler

P L E A S E  somebody help.  I have a design of mixed .gdf and .vhd
files that
were created in MaxPlusII, which I have imported it into Quartus II
v3.0 SP2.

What I am trying to do is to convert the complete design into VHDL
ONLY

The reason for doing this is so that i can do a functional simulation
of my design prior to synthesising it - synthesis currently takes 4
hours ! !

The problems I am having with Quartus are :- 

    - currently, the way i am creating a VHDL ONLY representation of
my design
    (without synth'ing) is by 'create HDL design file for current
file' on      every block diagram i have.  with quite a few block
diags this is getting VERY
    ANNOYING, slow and highly prone to error. does anybody know how to
do it better ?


     - generics dont work properly. declaring a parameter that defines
the
     generic works fine...so long as you dont want the generics to be
inhereted
     from the hierarchical level above - this is where the problems
arrise.  if
     i want the generic to be inhereted then i have to leave the
'value' box for
     the parameter empty, however this causes the generic clause to be
empty
     when i then create a HDL design file of my block diagram.