> I have just received USB platform cable, (I ordered it as I was not
> sure if I was going to be able to program the board with CF), is it
> possible to write and read the fpga IOs through it. In that case I
> would not need a parallel port to interface it?
>
Go and download an evaluation version of ChipScope Pro
http://www.xilinx.com/chipscope and try out the Virtual I/O (VIO)
core to handle your communication needs. You can set this up to
support many inputs and outputs into your design and in the GUI
you can group the signals in to buses with different radix types
including, binary, octal, hex, integer (with scaling factors), leds,
push buttons, toggle buttons and pulse chains for easy visuals.
The VIO core works well for limited data transfers, but if you need
more than try out the logic analyzer (ILA) core. This will work
will for capturing large amounts of data.
Ed McGettigan
--
Xilinx Inc.
Reply by EEngineer●July 26, 20062006-07-26
I have just received USB platform cable, (I ordered it as I was not
sure if I was going to be able to program the board with CF), is it
possible to write and read the fpga IOs through it. In that case I
would not need a parallel port to interface it?
Dan
Ed McGettigan wrote:
> EEngineer wrote:
> > Finally after two weeks I have configured the board for the first time.
> > I was misled that software update was performed every time I start the
> > ISE with WebUpdate, but that was not the case - after you mentioned SP
> > (it was not the one for Windows XP) I went to the update section of the
> > web site and installed SP 3. I am able to generate ACE files that work.
> >
> > Can I interface the board's J6 header single ended signal connections
> > with the parallel port on the PC with no buffer and what constrains
> > should be asserted for those pins?
> >
>
> I'm glad that you are moving forward with your design work.
>
> On the second item the answer is no as a parallel port is 5V and the
> IOs on the headers are 2.5V (or 3.3V if you move a jumper).
>
> Ed McGettigan
> --
> Xilinx Inc.
Reply by EEngineer●July 26, 20062006-07-26
IOs on the parallel port are TTL and 3.3V should be enough for
receiveing according to TTL specs?
Ed McGettigan wrote:
> EEngineer wrote:
> > Finally after two weeks I have configured the board for the first time.
> > I was misled that software update was performed every time I start the
> > ISE with WebUpdate, but that was not the case - after you mentioned SP
> > (it was not the one for Windows XP) I went to the update section of the
> > web site and installed SP 3. I am able to generate ACE files that work.
> >
> > Can I interface the board's J6 header single ended signal connections
> > with the parallel port on the PC with no buffer and what constrains
> > should be asserted for those pins?
> >
>
> I'm glad that you are moving forward with your design work.
>
> On the second item the answer is no as a parallel port is 5V and the
> IOs on the headers are 2.5V (or 3.3V if you move a jumper).
>
> Ed McGettigan
> --
> Xilinx Inc.
Reply by Ed McGettigan●July 25, 20062006-07-25
EEngineer wrote:
> Finally after two weeks I have configured the board for the first time.
> I was misled that software update was performed every time I start the
> ISE with WebUpdate, but that was not the case - after you mentioned SP
> (it was not the one for Windows XP) I went to the update section of the
> web site and installed SP 3. I am able to generate ACE files that work.
>
> Can I interface the board's J6 header single ended signal connections
> with the parallel port on the PC with no buffer and what constrains
> should be asserted for those pins?
>
I'm glad that you are moving forward with your design work.
On the second item the answer is no as a parallel port is 5V and the
IOs on the headers are 2.5V (or 3.3V if you move a jumper).
Ed McGettigan
--
Xilinx Inc.
Reply by EEngineer●July 25, 20062006-07-25
Finally after two weeks I have configured the board for the first time.
I was misled that software update was performed every time I start the
ISE with WebUpdate, but that was not the case - after you mentioned SP
(it was not the one for Windows XP) I went to the update section of the
web site and installed SP 3. I am able to generate ACE files that work.
Can I interface the board's J6 header single ended signal connections
with the parallel port on the PC with no buffer and what constrains
should be asserted for those pins?
Thanks for all your help,
Dan
Ed McGettigan wrote:
> EEngineer wrote:
> > I use:
> >
> > Service Pack 1
> >
>
> I would definitely try upgrading to Service Pack 3.
>
> Ed McGettigan
> --
> Xilinx Inc.
Reply by Ed McGettigan●July 24, 20062006-07-24
EEngineer wrote:
> I use:
>
> Service Pack 1
>
I would definitely try upgrading to Service Pack 3.
Ed McGettigan
--
Xilinx Inc.
> EEngineer wrote:
> > What is the ACE file size that you created? All the demos are 1686KB
> > and the new ACE created with iMPACT is 1674KB.
>
> The file that I generated was 1686KB using the 8.1.03i (Service Pack 3)
> software. You can find out which version you are using the "Help -> About"
> menu.
>
> Ed
Reply by EEngineer●July 24, 20062006-07-24
I am using
Release Version: 8.1i
Application Version: I.24
I always get 1674KB ACE file, maybe that points to some problem?
Ed McGettigan wrote:
> EEngineer wrote:
> > What is the ACE file size that you created? All the demos are 1686KB
> > and the new ACE created with iMPACT is 1674KB.
>
> The file that I generated was 1686KB using the 8.1.03i (Service Pack 3)
> software. You can find out which version you are using the "Help -> About"
> menu.
>
> Ed
Reply by Ed McGettigan●July 24, 20062006-07-24
EEngineer wrote:
> What is the ACE file size that you created? All the demos are 1686KB
> and the new ACE created with iMPACT is 1674KB.
The file that I generated was 1686KB using the 8.1.03i (Service Pack 3)
software. You can find out which version you are using the "Help -> About"
menu.
Ed